RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration. Guo, L., Maidee, P., Zhou, Y., Lavin, C., Hung, E., Li, W., Lau, J., Qiao, W., Chi, Y., Song, L., Xiao, Y., Kaviani, A., Zhang, Z., & Cong, J. ACM Trans. Reconfigurable Technol. Syst., 16(4):59:1-59:30, 12, 2023.
RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration. [link]Link  RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration. [link]Paper  bibtex   
@article{journals/trets/GuoMZLHLLQCSXKZC23,
  added-at = {2025-01-19T00:00:00.000+0100},
  author = {Guo, Licheng and Maidee, Pongstorn and Zhou, Yun and Lavin, Chris and Hung, Eddie and Li, Wuxi and Lau, Jason and Qiao, Weikang and Chi, Yuze and Song, Linghao and Xiao, Yuanlong and Kaviani, Alireza and Zhang, Zhiru and Cong, Jason},
  biburl = {https://www.bibsonomy.org/bibtex/2d31c0250cf789b6879886d1570ded349/dblp},
  ee = {https://www.wikidata.org/entity/Q130819848},
  interhash = {471a9852103ab537c33638d6fc8fb9c5},
  intrahash = {d31c0250cf789b6879886d1570ded349},
  journal = {ACM Trans. Reconfigurable Technol. Syst.},
  keywords = {dblp},
  month = {12},
  number = 4,
  pages = {59:1-59:30},
  timestamp = {2025-01-27T09:14:11.000+0100},
  title = {RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration.},
  url = {http://dblp.uni-trier.de/db/journals/trets/trets16.html#GuoMZLHLLQCSXKZC23},
  volume = 16,
  year = 2023
}

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