RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration. Guo, L., Maidee, P., Zhou, Y., Lavin, C., Hung, E., Li, W., Lau, J., Qiao, W., Chi, Y., Song, L., Xiao, Y., Kaviani, A., Zhang, Z., & Cong, J. ACM Trans. Reconfigurable Technol. Syst., 16(4):59:1-59:30, 12, 2023.
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Paper bibtex @article{journals/trets/GuoMZLHLLQCSXKZC23,
added-at = {2025-01-19T00:00:00.000+0100},
author = {Guo, Licheng and Maidee, Pongstorn and Zhou, Yun and Lavin, Chris and Hung, Eddie and Li, Wuxi and Lau, Jason and Qiao, Weikang and Chi, Yuze and Song, Linghao and Xiao, Yuanlong and Kaviani, Alireza and Zhang, Zhiru and Cong, Jason},
biburl = {https://www.bibsonomy.org/bibtex/2d31c0250cf789b6879886d1570ded349/dblp},
ee = {https://www.wikidata.org/entity/Q130819848},
interhash = {471a9852103ab537c33638d6fc8fb9c5},
intrahash = {d31c0250cf789b6879886d1570ded349},
journal = {ACM Trans. Reconfigurable Technol. Syst.},
keywords = {dblp},
month = {12},
number = 4,
pages = {59:1-59:30},
timestamp = {2025-01-27T09:14:11.000+0100},
title = {RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration.},
url = {http://dblp.uni-trier.de/db/journals/trets/trets16.html#GuoMZLHLLQCSXKZC23},
volume = 16,
year = 2023
}
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{"_id":"MDwQswxCCxbdRaT6u","bibbaseid":"guo-maidee-zhou-lavin-hung-li-lau-qiao-etal-rapidstream20automatedparallelimplementationoflatencyinsensitivefpgadesignsthroughpartialreconfiguration-2023","author_short":["Guo, L.","Maidee, P.","Zhou, Y.","Lavin, C.","Hung, E.","Li, W.","Lau, J.","Qiao, W.","Chi, Y.","Song, L.","Xiao, Y.","Kaviani, A.","Zhang, Z.","Cong, J."],"bibdata":{"bibtype":"article","type":"article","added-at":"2025-01-19T00:00:00.000+0100","author":[{"propositions":[],"lastnames":["Guo"],"firstnames":["Licheng"],"suffixes":[]},{"propositions":[],"lastnames":["Maidee"],"firstnames":["Pongstorn"],"suffixes":[]},{"propositions":[],"lastnames":["Zhou"],"firstnames":["Yun"],"suffixes":[]},{"propositions":[],"lastnames":["Lavin"],"firstnames":["Chris"],"suffixes":[]},{"propositions":[],"lastnames":["Hung"],"firstnames":["Eddie"],"suffixes":[]},{"propositions":[],"lastnames":["Li"],"firstnames":["Wuxi"],"suffixes":[]},{"propositions":[],"lastnames":["Lau"],"firstnames":["Jason"],"suffixes":[]},{"propositions":[],"lastnames":["Qiao"],"firstnames":["Weikang"],"suffixes":[]},{"propositions":[],"lastnames":["Chi"],"firstnames":["Yuze"],"suffixes":[]},{"propositions":[],"lastnames":["Song"],"firstnames":["Linghao"],"suffixes":[]},{"propositions":[],"lastnames":["Xiao"],"firstnames":["Yuanlong"],"suffixes":[]},{"propositions":[],"lastnames":["Kaviani"],"firstnames":["Alireza"],"suffixes":[]},{"propositions":[],"lastnames":["Zhang"],"firstnames":["Zhiru"],"suffixes":[]},{"propositions":[],"lastnames":["Cong"],"firstnames":["Jason"],"suffixes":[]}],"biburl":"https://www.bibsonomy.org/bibtex/2d31c0250cf789b6879886d1570ded349/dblp","ee":"https://www.wikidata.org/entity/Q130819848","interhash":"471a9852103ab537c33638d6fc8fb9c5","intrahash":"d31c0250cf789b6879886d1570ded349","journal":"ACM Trans. Reconfigurable Technol. Syst.","keywords":"dblp","month":"12","number":"4","pages":"59:1-59:30","timestamp":"2025-01-27T09:14:11.000+0100","title":"RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration.","url":"http://dblp.uni-trier.de/db/journals/trets/trets16.html#GuoMZLHLLQCSXKZC23","volume":"16","year":"2023","bibtex":"@article{journals/trets/GuoMZLHLLQCSXKZC23,\n added-at = {2025-01-19T00:00:00.000+0100},\n author = {Guo, Licheng and Maidee, Pongstorn and Zhou, Yun and Lavin, Chris and Hung, Eddie and Li, Wuxi and Lau, Jason and Qiao, Weikang and Chi, Yuze and Song, Linghao and Xiao, Yuanlong and Kaviani, Alireza and Zhang, Zhiru and Cong, Jason},\n biburl = {https://www.bibsonomy.org/bibtex/2d31c0250cf789b6879886d1570ded349/dblp},\n ee = {https://www.wikidata.org/entity/Q130819848},\n interhash = {471a9852103ab537c33638d6fc8fb9c5},\n intrahash = {d31c0250cf789b6879886d1570ded349},\n journal = {ACM Trans. Reconfigurable Technol. Syst.},\n keywords = {dblp},\n month = {12},\n number = 4,\n pages = {59:1-59:30},\n timestamp = {2025-01-27T09:14:11.000+0100},\n title = {RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration.},\n url = {http://dblp.uni-trier.de/db/journals/trets/trets16.html#GuoMZLHLLQCSXKZC23},\n volume = 16,\n year = 2023\n}\n\n","author_short":["Guo, L.","Maidee, P.","Zhou, Y.","Lavin, C.","Hung, E.","Li, W.","Lau, J.","Qiao, W.","Chi, Y.","Song, L.","Xiao, Y.","Kaviani, A.","Zhang, Z.","Cong, J."],"key":"journals/trets/GuoMZLHLLQCSXKZC23","id":"journals/trets/GuoMZLHLLQCSXKZC23","bibbaseid":"guo-maidee-zhou-lavin-hung-li-lau-qiao-etal-rapidstream20automatedparallelimplementationoflatencyinsensitivefpgadesignsthroughpartialreconfiguration-2023","role":"author","urls":{"Link":"https://www.wikidata.org/entity/Q130819848","Paper":"http://dblp.uni-trier.de/db/journals/trets/trets16.html#GuoMZLHLLQCSXKZC23"},"keyword":["dblp"],"metadata":{"authorlinks":{}},"downloads":0,"html":""},"bibtype":"article","biburl":"http://www.bibsonomy.org/bib/author/Jason?items=1000","dataSources":["miMWJWjn4sT6Q3GDs"],"keywords":["dblp"],"search_terms":["rapidstream","automated","parallel","implementation","latency","insensitive","fpga","designs","through","partial","reconfiguration","guo","maidee","zhou","lavin","hung","li","lau","qiao","chi","song","xiao","kaviani","zhang","cong"],"title":"RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration.","year":2023}