Scalable All-Analog LDOs With Reduced Input Offset Variability Using Digital Synthesis Flow in 65-nm CMOS. Gupta, S., Li, S., & Calhoun, B. H. IEEE transactions on very large scale integration (VLSI) systems (Print), 2024.
Scalable All-Analog LDOs With Reduced Input Offset Variability Using Digital Synthesis Flow in 65-nm CMOS [link]Paper  bibtex   
@article{577,
  author = {Sonam Gupta and Shuo Li and Benton H. Calhoun},
  title = {Scalable All-Analog LDOs With Reduced Input Offset Variability Using Digital Synthesis Flow in 65-nm CMOS},
  year = {2024},
  journal = {IEEE transactions on very large scale integration (VLSI) systems (Print)},
  url = {https://doi.org/10.1109/tvlsi.2023.3328978}
}

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