{"_id":"qADceryFJJDakWjcq","bibbaseid":"gupta-li-calhoun-scalableallanalogldoswithreducedinputoffsetvariabilityusingdigitalsynthesisflowin65nmcmos-2024","author_short":["Gupta, S.","Li, S.","Calhoun, B. H."],"bibdata":{"bibtype":"article","type":"article","author":[{"firstnames":["Sonam"],"propositions":[],"lastnames":["Gupta"],"suffixes":[]},{"firstnames":["Shuo"],"propositions":[],"lastnames":["Li"],"suffixes":[]},{"firstnames":["Benton","H."],"propositions":[],"lastnames":["Calhoun"],"suffixes":[]}],"title":"Scalable All-Analog LDOs With Reduced Input Offset Variability Using Digital Synthesis Flow in 65-nm CMOS","year":"2024","journal":"IEEE transactions on very large scale integration (VLSI) systems (Print)","url":"https://doi.org/10.1109/tvlsi.2023.3328978","bibtex":"@article{577,\n author = {Sonam Gupta and Shuo Li and Benton H. Calhoun},\n title = {Scalable All-Analog LDOs With Reduced Input Offset Variability Using Digital Synthesis Flow in 65-nm CMOS},\n year = {2024},\n journal = {IEEE transactions on very large scale integration (VLSI) systems (Print)},\n url = {https://doi.org/10.1109/tvlsi.2023.3328978}\n}\n\n","author_short":["Gupta, S.","Li, S.","Calhoun, B. H."],"key":"577","id":"577","bibbaseid":"gupta-li-calhoun-scalableallanalogldoswithreducedinputoffsetvariabilityusingdigitalsynthesisflowin65nmcmos-2024","role":"author","urls":{"Paper":"https://doi.org/10.1109/tvlsi.2023.3328978"},"metadata":{"authorlinks":{}}},"bibtype":"article","biburl":"https://bibbase.org/f/fFERMKNwKyHLsDPJ3/Link_Lab_Publications.bib","dataSources":["mwAui9iKniQyhTc49","RbCkvcfqfbgtxTyNT","PbrtYBE4kqkc5ZtpJ"],"keywords":[],"search_terms":["scalable","analog","ldos","reduced","input","offset","variability","using","digital","synthesis","flow","cmos","gupta","li","calhoun"],"title":"Scalable All-Analog LDOs With Reduced Input Offset Variability Using Digital Synthesis Flow in 65-nm CMOS","year":2024}