Bit error rates of flip-flop operations with AND gate functionality using a 1.55-µm polarization bistable VCSEL. Hayashi, D., Nakao, K., Katayama, T., & Kawaguchi, H. IEICE Electron. Express, 12(13):20150479, 2015.
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Paper bibtex @article{journals/ieiceee/HayashiNKK15,
added-at = {2025-03-03T00:00:00.000+0100},
author = {Hayashi, Daisuke and Nakao, Kazuya and Katayama, Takeo and Kawaguchi, Hitoshi},
biburl = {https://www.bibsonomy.org/bibtex/2462ff5617c74a932dbc3f890528850e8/dblp},
ee = {https://doi.org/10.1587/elex.12.20150479},
interhash = {345cb52509c44e8e5d90f7149827c2da},
intrahash = {462ff5617c74a932dbc3f890528850e8},
journal = {IEICE Electron. Express},
keywords = {dblp},
number = 13,
pages = 20150479,
timestamp = {2025-04-01T15:12:08.000+0200},
title = {Bit error rates of flip-flop operations with AND gate functionality using a 1.55-µm polarization bistable VCSEL.},
url = {http://dblp.uni-trier.de/db/journals/ieiceee/ieiceee12.html#HayashiNKK15},
volume = 12,
year = 2015
}
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