A Fully Autonomous Integrated Interface Circuit for Piezoelectric Harvesters. Hehn, T., Hagedorn, F., Maurath, D., Marinkovic, D., Kuehne, I., Frey, A., & Manoli, Y. IEEE Journal of Solid-State Circuits, 47(9):2185–2198, September, 2012. doi abstract bibtex This paper presents a fully autonomous, adaptive pulsed synchronous charge extractor (PSCE) circuit optimized for piezoelectric harvesters (PEHs) which have a wide output voltage range 1.3-20 V. The PSCE chip fabricated in a 0.35 μm CMOS process is supplied exclusively by the buffer capacitor where the harvested energy is stored in. Due to the low power consumption, the chip can handle a minimum PEH output power of 5.7 μW. The system performs a startup from an uncharged buffer capacitor and operates in the adaptive mode at storage buffer voltages from 1.4 V to 5 V. By reducing the series resistance losses, the implementation of an improved switching technique increases the extracted power by up to 20% compared to the formerly presented Synchronous Electric Charge Extraction (SECE) technique and enables the chip efficiency to reach values of up to 85%. Compared to a low-voltage-drop passive full-wave rectifier, the PSCE chip increases the extracted power to 123% when the PEH is driven at resonance and to 206% at off-resonance.
@article{hehn_fully_2012,
title = {A {Fully} {Autonomous} {Integrated} {Interface} {Circuit} for {Piezoelectric} {Harvesters}},
volume = {47},
issn = {0018-9200},
doi = {10.1109/JSSC.2012.2200530},
abstract = {This paper presents a fully autonomous, adaptive pulsed synchronous charge extractor (PSCE) circuit optimized for piezoelectric harvesters (PEHs) which have a wide output voltage range 1.3-20 V. The PSCE chip fabricated in a 0.35 μm CMOS process is supplied exclusively by the buffer capacitor where the harvested energy is stored in. Due to the low power consumption, the chip can handle a minimum PEH output power of 5.7 μW. The system performs a startup from an uncharged buffer capacitor and operates in the adaptive mode at storage buffer voltages from 1.4 V to 5 V. By reducing the series resistance losses, the implementation of an improved switching technique increases the extracted power by up to 20\% compared to the formerly presented Synchronous Electric Charge Extraction (SECE) technique and enables the chip efficiency to reach values of up to 85\%. Compared to a low-voltage-drop passive full-wave rectifier, the PSCE chip increases the extracted power to 123\% when the PEH is driven at resonance and to 206\% at off-resonance.},
number = {9},
journal = {IEEE Journal of Solid-State Circuits},
author = {Hehn, T. and Hagedorn, F. and Maurath, D. and Marinkovic, D. and Kuehne, I. and Frey, A. and Manoli, Y.},
month = sep,
year = {2012},
pages = {2185--2198}
}
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