Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only). Hoang, A. & Fujino, T. In Proceedings of Field Programmable Gate Arrays (FPGA), pages 266-267, 2013.
Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only) [link]Paper  bibtex   
@inproceedings{ dblp1954615,
  title = {Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only)},
  author = {Anh-Tuan Hoang and Takeshi Fujino},
  author_short = {Hoang, A. and Fujino, T.},
  bibtype = {inproceedings},
  type = {inproceedings},
  year = {2013},
  key = {dblp1954615},
  id = {dblp1954615},
  biburl = {http://www.dblp.org/rec/bibtex/conf/fpga/HoangF13},
  url = {http://doi.acm.org/10.1145/2435264.2435315},
  conference = {FPGA},
  pages = {266-267},
  text = {FPGA 2013:266-267},
  booktitle = {Proceedings of Field Programmable Gate Arrays (FPGA)}
}

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