Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGA. Hoang, A. & Fujino, T. In Proceedings of Field Programmable Gate Arrays (FPGA), pages 1-10, 2012. Paper bibtex @inproceedings{ dblp2187819,
title = {Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGA},
author = {Anh-Tuan Hoang and Takeshi Fujino},
author_short = {Hoang, A. and Fujino, T.},
bibtype = {inproceedings},
type = {inproceedings},
year = {2012},
key = {dblp2187819},
id = {dblp2187819},
biburl = {http://www.dblp.org/rec/bibtex/conf/fpga/HoangF12},
url = {http://doi.acm.org/10.1145/2145694.2145696},
conference = {FPGA},
pages = {1-10},
text = {FPGA 2012:1-10},
booktitle = {Proceedings of Field Programmable Gate Arrays (FPGA)}
}
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