200 MS/s ADC implemented in a FPGA employing TDCs. Homulle, H., Regazzoni, F., & Charbon, E. In Constantinides, G. A. & Chen, D., editors, Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, February 22-24, 2015, pages 228–235, 2015. ACM.
200 MS/s ADC implemented in a FPGA employing TDCs [link]Paper  doi  bibtex   
@inproceedings{DBLP:conf/fpga/HomulleRC15,
  author    = {Harald Homulle and
               Francesco Regazzoni and
               Edoardo Charbon},
  editor    = {George A. Constantinides and
               Deming Chen},
  title     = {200 MS/s {ADC} implemented in a {FPGA} employing TDCs},
  booktitle = {Proceedings of the 2015 {ACM/SIGDA} International Symposium on Field-Programmable
               Gate Arrays, Monterey, CA, USA, February 22-24, 2015},
  pages     = {228--235},
  publisher = {{ACM}},
  year      = {2015},
  url       = {https://doi.org/10.1145/2684746.2689070},
  doi       = {10.1145/2684746.2689070},
  timestamp = {Tue, 31 Mar 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/fpga/HomulleRC15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

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