Static scheduling of a Time-Triggered Network-on-Chip based on SMT solving. Huang, J., Blech, J. O., Raabe, A., Buckl, C., & Knoll, A. In 2012 Design, Automation Test in Europe Conference Exhibition (DATE), pages 509–514, March, 2012. ISSN: 1530-1591doi abstract bibtex Time-Triggered Network-on-Chip (TTNoC) is a networking concept aiming at providing both predictable and high-throughput communication for modern multiprocessor systems. The message scheduling is one of the major design challenges in TTNoC-based systems. The designers not only need to allocate time slots but also have to assign communication routes for all messages. This paper tackles the TTNoC scheduling problem and presents an approach based on Satisfiability Modulo Theories (SMT) solving. We first formulate the complete problem as an SMT instance, which can always compute a feasible solution if exists. Thereafter, we propose an incremental approach that integrates SMT solving into classical heuristic algorithms. The experimental results show that the heuristic scales significantly better with only minor loss of performance.
@inproceedings{huang2012Static,
title = {Static scheduling of a {Time}-{Triggered} {Network}-on-{Chip} based on {SMT} solving},
doi = {10.1109/DATE.2012.6176522},
abstract = {Time-Triggered Network-on-Chip (TTNoC) is a networking concept aiming at providing both predictable and high-throughput communication for modern multiprocessor systems. The message scheduling is one of the major design challenges in TTNoC-based systems. The designers not only need to allocate time slots but also have to assign communication routes for all messages. This paper tackles the TTNoC scheduling problem and presents an approach based on Satisfiability Modulo Theories (SMT) solving. We first formulate the complete problem as an SMT instance, which can always compute a feasible solution if exists. Thereafter, we propose an incremental approach that integrates SMT solving into classical heuristic algorithms. The experimental results show that the heuristic scales significantly better with only minor loss of performance.},
booktitle = {2012 {Design}, {Automation} {Test} in {Europe} {Conference} {Exhibition} ({DATE})},
author = {Huang, Jia and Blech, Jan Olaf and Raabe, Andreas and Buckl, Christian and Knoll, Alois},
month = mar,
year = {2012},
note = {ISSN: 1530-1591},
keywords = {Computer architecture, Resource management, Routing, SMT solving, Schedules, Scheduling, Strips, TTNoC-based systems, Time division multiple access, communication route assignment, computability, heuristic algorithms, high-throughput communication, message passing, message scheduling, modern multiprocessor systems, multiprocessing systems, network-on-chip, networking concept, processor scheduling, resource allocation, satisfiability modulo theory solving, static scheduling, time slot allocation, time-triggered network-on-chip},
pages = {509--514}
}
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