21.3 A Fully Integrated 2.7µW -70.2dBm-Sensitivity Wake-Up Receiver with Charge-Domain Analog Front-End, -16.5dB-SIR, FEC and Cryptographic Checksum. Huang, K., Brown, J. K., Collins, N. R., Sawyer, R. K., Yahya, F. B., Wang, A., Roberts, N. E., Calhoun, B. H., & Wentzloff, D. D. 2021.
bibtex   
@article{917,
  author = {Kuo-Ken Huang and Jonathan K. Brown and Nicholas R. Collins and Richard K. Sawyer and Farah B. Yahya and Alice Wang and Nathan E. Roberts and Benton H. Calhoun and David D. Wentzloff},
  title = {21.3 A Fully Integrated 2.7µW -70.2dBm-Sensitivity Wake-Up Receiver with Charge-Domain Analog Front-End, -16.5dB-SIR, FEC and Cryptographic Checksum},
  year = {2021}
}

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