In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays. Hui, Y., Li, Q., Wang, L., Liu, C., Zhang, D., & Miao, X. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2024.
bibtex   
@article{hui2024memory,
  title={In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays},
  author={Hui, Yajuan and Li, Qingzhen and Wang, Leimin and Liu, Cheng and Zhang, Deming and Miao, Xiangshui},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2024},
  publisher={IEEE}
}

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