LV CMOS high speed analog multiplier. Hwang, C., Hyogo, A., Ismail, M., Kim, H., & Moon, G. In Midwest Symposium on Circuits and Systems, volume 2, 1997. abstract bibtex In this paper we propose a new low voltage high-speed CMOS composite transistor. This new transistor with a 3 dB bandwidth of 444 MHz lowers supply voltage down to |V t |+2 V ds,sat and extends input voltage operating range to 1.8 V with a 3 V supply. These features together with the two high input impedance terminals provided by the composite transistor leads to the design of a high-speed four quadrant analog multiplier. All simulations have been carried out using MOSIS 2 μm N-well process with a 3 V supply. The results show that the multiplier can operate with a maximum differential input of 1 V pp and ω--3 dB$/ of 305 MHz.
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title = {LV CMOS high speed analog multiplier},
type = {inProceedings},
year = {1997},
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abstract = {In this paper we propose a new low voltage high-speed CMOS composite transistor. This new transistor with a 3 dB bandwidth of 444 MHz lowers supply voltage down to |V t |+2 V ds,sat and extends input voltage operating range to 1.8 V with a 3 V supply. These features together with the two high input impedance terminals provided by the composite transistor leads to the design of a high-speed four quadrant analog multiplier. All simulations have been carried out using MOSIS 2 μm N-well process with a 3 V supply. The results show that the multiplier can operate with a maximum differential input of 1 V pp and ω--3 dB$/ of 305 MHz.},
bibtype = {inProceedings},
author = {Hwang, Changku and Hyogo, Akira and Ismail, Mohammed and Kim, Hong-sun and Moon, Gyu},
booktitle = {Midwest Symposium on Circuits and Systems}
}
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