@article{
 title = {Low voltage high-speed CMOS square-law composite transistor cell},
 type = {article},
 year = {2000},
 identifiers = {[object Object]},
 volume = {25},
 id = {45f1046d-a9f6-3fd6-9630-51a7036f9eaa},
 created = {2017-12-04T05:35:04.117Z},
 file_attached = {false},
 profile_id = {99d7e05e-a704-3549-ada2-dfc74a2d55ec},
 last_modified = {2017-12-04T05:35:04.117Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to |V t | + 2 V ds,sat and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2 μm N-well process with a 3V supply are given.},
 bibtype = {article},
 author = {Hwang, C. and Hyogo, A. and Kim, H.-S. and Ismail, M. and Sekine, K.},
 journal = {Analog Integrated Circuits and Signal Processing},
 number = {3}
}

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