Dedicated Hardware Accelerators for Processing of Sparse Matrices and Vectors: A Survey. Isaac-Chassande, V., Evans, A., Durand, Y., & Rousseau, F. ACM Trans. Archit. Code Optim., 21(2):27, 06, 2024.
Dedicated Hardware Accelerators for Processing of Sparse Matrices and Vectors: A Survey. [link]Link  Dedicated Hardware Accelerators for Processing of Sparse Matrices and Vectors: A Survey. [link]Paper  bibtex   
@article{journals/taco/IsaacChassandeEDR24,
  added-at = {2025-01-19T00:00:00.000+0100},
  author = {Isaac-Chassande, Valentin and Evans, Adrian and Durand, Yves and Rousseau, Frédéric},
  biburl = {https://www.bibsonomy.org/bibtex/2296ddb485818f32c83da990e010a99df/dblp},
  ee = {https://www.wikidata.org/entity/Q129749502},
  interhash = {f81ce3e316d14d9668038b065223bf39},
  intrahash = {296ddb485818f32c83da990e010a99df},
  journal = {ACM Trans. Archit. Code Optim.},
  keywords = {dblp},
  month = {06},
  number = 2,
  pages = 27,
  timestamp = {2025-01-27T09:23:11.000+0100},
  title = {Dedicated Hardware Accelerators for Processing of Sparse Matrices and Vectors: A Survey.},
  url = {http://dblp.uni-trier.de/db/journals/taco/taco21.html#IsaacChassandeEDR24},
  volume = 21,
  year = 2024
}

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