Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit. Ito, H., Shiozaki, M., Hoang, A., & Fujino, T. In Proceedings of Digital Systems Design (DSD), pages 735-738, 2012.
Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit [link]Paper  bibtex   
@inproceedings{ dblp2172401,
  title = {Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit},
  author = {Hiroki Ito and Mitsuru Shiozaki and Anh-Tuan Hoang and Takeshi Fujino},
  author_short = {Ito, H. and Shiozaki, M. and Hoang, A. and Fujino, T.},
  bibtype = {inproceedings},
  type = {inproceedings},
  year = {2012},
  key = {dblp2172401},
  id = {dblp2172401},
  biburl = {http://www.dblp.org/rec/bibtex/conf/dsd/ItoSHF12},
  url = {http://dx.doi.org/10.1109/DSD.2012.46},
  conference = {DSD},
  pages = {735-738},
  text = {DSD 2012:735-738},
  booktitle = {Proceedings of Digital Systems Design (DSD)}
}

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