Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit. Ito, H., Shiozaki, M., Hoang, A., & Fujino, T. In Proceedings of Digital Systems Design (DSD), pages 735-738, 2012.
Paper bibtex @inproceedings{ dblp2172401,
title = {Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit},
author = {Hiroki Ito and Mitsuru Shiozaki and Anh-Tuan Hoang and Takeshi Fujino},
author_short = {Ito, H. and Shiozaki, M. and Hoang, A. and Fujino, T.},
bibtype = {inproceedings},
type = {inproceedings},
year = {2012},
key = {dblp2172401},
id = {dblp2172401},
biburl = {http://www.dblp.org/rec/bibtex/conf/dsd/ItoSHF12},
url = {http://dx.doi.org/10.1109/DSD.2012.46},
conference = {DSD},
pages = {735-738},
text = {DSD 2012:735-738},
booktitle = {Proceedings of Digital Systems Design (DSD)}
}
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{"_id":"qfT26FEqRcQKC2pHj","bibbaseid":"ito-shiozaki-hoang-fujino-efficientdparesistanceverificationmethodwithsmallernumberofpowertracesonaescryptographiccircuit-2012","downloads":0,"creationDate":"2015-06-12T22:13:33.816Z","title":"Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit","author_short":["Ito, H.","Shiozaki, M.","Hoang, A.","Fujino, T."],"year":2012,"bibtype":"inproceedings","biburl":"http://www.dblp.org/rec/bibtex/conf/dsd/ItoSHF12","bibdata":{"title":"Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit","author":["Hiroki Ito","Mitsuru Shiozaki","Anh-Tuan Hoang","Takeshi Fujino"],"author_short":["Ito, H.","Shiozaki, M.","Hoang, A.","Fujino, T."],"bibtype":"inproceedings","type":"inproceedings","year":"2012","key":"dblp2172401","id":"dblp2172401","biburl":"http://www.dblp.org/rec/bibtex/conf/dsd/ItoSHF12","url":"http://dx.doi.org/10.1109/DSD.2012.46","conference":"DSD","pages":"735-738","text":"DSD 2012:735-738","booktitle":"Proceedings of Digital Systems Design (DSD)","bibtex":"@inproceedings{ dblp2172401,\n title = {Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit},\n author = {Hiroki Ito and Mitsuru Shiozaki and Anh-Tuan Hoang and Takeshi Fujino},\n author_short = {Ito, H. and Shiozaki, M. and Hoang, A. and Fujino, T.},\n bibtype = {inproceedings},\n type = {inproceedings},\n year = {2012},\n key = {dblp2172401},\n id = {dblp2172401},\n biburl = {http://www.dblp.org/rec/bibtex/conf/dsd/ItoSHF12},\n url = {http://dx.doi.org/10.1109/DSD.2012.46},\n conference = {DSD},\n pages = {735-738},\n text = {DSD 2012:735-738},\n booktitle = {Proceedings of Digital Systems Design (DSD)}\n}","bibbaseid":"ito-shiozaki-hoang-fujino-efficientdparesistanceverificationmethodwithsmallernumberofpowertracesonaescryptographiccircuit-2012","role":"author","urls":{"Paper":"http://dx.doi.org/10.1109/DSD.2012.46"},"downloads":0},"search_terms":["efficient","dpa","resistance","verification","method","smaller","number","power","traces","aes","cryptographic","circuit","ito","shiozaki","hoang","fujino"],"keywords":[],"authorIDs":[],"dataSources":["iwKcmiaXKEw7pxDE6"]}