Reducing transistor count in clocked standard cells with ambipolar double-gate FETs. Jabeur, K., Navarro, D., O'Connor, I., Gaillardon, P., Jamaa, M. H. B., & Clermidy, F. In 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010, Anaheim, CA, USA, June 17-18, 2010, pages 47–52, 2010. Paper doi bibtex @inproceedings{DBLP:conf/nanoarch/JabeurNOGJC10,
author = {Kotb Jabeur and
David Navarro and
Ian O'Connor and
Pierre{-}Emmanuel Gaillardon and
M. Haykel Ben Jamaa and
Fabien Clermidy},
title = {Reducing transistor count in clocked standard cells with ambipolar
double-gate FETs},
booktitle = {2010 {IEEE/ACM} International Symposium on Nanoscale Architectures,
{NANOARCH} 2010, Anaheim, CA, USA, June 17-18, 2010},
pages = {47--52},
year = {2010},
crossref = {DBLP:conf/nanoarch/2010},
url = {https://doi.org/10.1109/NANOARCH.2010.5510928},
doi = {10.1109/NANOARCH.2010.5510928},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/bib/conf/nanoarch/JabeurNOGJC10},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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