Microarchitecture evaluation with floorplanning and interconnect pipelining. Jagannathan, A., Yang, H. H., Konigsfeld, K., Milliron, D., Mohan, M., Romesis, M., Reinman, G., & Cong, J. In ASP-DAC, pages 8-15, 2005. ACM Press.
Microarchitecture evaluation with floorplanning and interconnect pipelining. [link]Link  Microarchitecture evaluation with floorplanning and interconnect pipelining. [link]Paper  bibtex   
@inproceedings{conf/aspdac/JagannathanYKMMRRC05,
  added-at = {2025-01-19T00:00:00.000+0100},
  author = {Jagannathan, Ashok and Yang, Hannah Honghua and Konigsfeld, Kris and Milliron, Dan and Mohan, Mosur and Romesis, Michail and Reinman, Glenn and Cong, Jason},
  biburl = {https://www.bibsonomy.org/bibtex/256f3e7d76acd9a10113947fa4febace6/dblp},
  booktitle = {ASP-DAC},
  crossref = {conf/aspdac/2005},
  editor = {Tang, Tingao},
  ee = {https://www.wikidata.org/entity/Q130984372},
  interhash = {c9f92c6be4c6577721d57344f6ae9bd6},
  intrahash = {56f3e7d76acd9a10113947fa4febace6},
  isbn = {0-7803-8737-6},
  keywords = {dblp},
  pages = {8-15},
  publisher = {ACM Press},
  timestamp = {2025-01-27T10:08:03.000+0100},
  title = {Microarchitecture evaluation with floorplanning and interconnect pipelining.},
  url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac2005.html#JagannathanYKMMRRC05},
  year = 2005
}

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