Analyzing the impact of augmented transistor NMOS configuration on parameters of 4×1 multiplexer. Jain, P. & Joshi, A. Radioelectronics and Communications Systems, 2018. doi abstract bibtex © Allerton Press, Inc., 2018 and P. Jain, A.M. Joshi, 2018, published in Izvestiya Vysshikh Uchebnykh Zavedenii. This paper represents the power and delay analysis of 4×1 multiplexer based on Augmented Transistor NMOS (AT-NMOS) configurations. Transistor’s total channel width at multiple levels are considered to determine the leakage power and delay performance at 45 nm technology. It is evaluated that the performance parameter is improved in the proposed design based on Augmented Shorted Gate-Source PMOS with NMOS (ASG-S PMOS-NMOS) configuration as compared to the 4×1 multiplexer based on Static Threshold AT-NMOS (ST-ATNMOS) configuration. Using this combination, we obtain the desired performance parameters of the design. In this paper, two types of 4×1 multiplexer models are introduced. It is shown that the leakage power can be largely reduced. The delay performance is also improved up to 5% at 1 V power supply under consideration of multiple levels of transistor’s channel width due to evaluation of different AT-NMOS configurations based 4×1 multiplexer models. The simulation work has been carried out using the Cadence Analog Virtuoso Spectre Simulator at 45 nm CMOS technology.
@article{
title = {Analyzing the impact of augmented transistor NMOS configuration on parameters of 4×1 multiplexer},
type = {article},
year = {2018},
volume = {61},
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abstract = {© Allerton Press, Inc., 2018 and P. Jain, A.M. Joshi, 2018, published in Izvestiya Vysshikh Uchebnykh Zavedenii. This paper represents the power and delay analysis of 4×1 multiplexer based on Augmented Transistor NMOS (AT-NMOS) configurations. Transistor’s total channel width at multiple levels are considered to determine the leakage power and delay performance at 45 nm technology. It is evaluated that the performance parameter is improved in the proposed design based on Augmented Shorted Gate-Source PMOS with NMOS (ASG-S PMOS-NMOS) configuration as compared to the 4×1 multiplexer based on Static Threshold AT-NMOS (ST-ATNMOS) configuration. Using this combination, we obtain the desired performance parameters of the design. In this paper, two types of 4×1 multiplexer models are introduced. It is shown that the leakage power can be largely reduced. The delay performance is also improved up to 5% at 1 V power supply under consideration of multiple levels of transistor’s channel width due to evaluation of different AT-NMOS configurations based 4×1 multiplexer models. The simulation work has been carried out using the Cadence Analog Virtuoso Spectre Simulator at 45 nm CMOS technology.},
bibtype = {article},
author = {Jain, P. and Joshi, A.M.},
doi = {10.3103/S0735272718030044},
journal = {Radioelectronics and Communications Systems},
number = {3}
}
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