Full-Wave Bridge Rectifier with CMOS Pass Transistors Configuration. Jain, P. & Joshi, A. Journal of Circuits, Systems and Computers, 2018. doi abstract bibtex © 2018 World Scientific Publishing Company. An effortless, more efficient full-wave bridge rectifier is introduced with minimum distortion. Efficient and exploratory combinations of CMOS logic are not only utilized to design full-wave bridge rectifier, but also as pass transistors configurations at the input. The particular CMOS logic (used to design core rectifier circuit) is a collective form of SDG-NMOS and SGS-PMOS. SDG-NMOS refers to a shorted drain gate n-channel metal oxide semiconductor. SGS-PMOS refers to shorted gate to source p-channel metal oxide semiconductor. Due to the utilization of renovated MOS configuration after the replacement of the diode, the efficiency of the full-wave bridge rectifier is increased up to 11% compared to p-n junction diode based full wave bridge rectifier. The proposed full wave bridge rectifier is a comparably low power circuit. The proposed CMOS based full-wave bridge rectifier is optimized at 45-nm CMOS technology. Cadence experimental simulation and implementations of the leakage power and efficiency demonstrate better consistency through the proposed circuit.
@article{
title = {Full-Wave Bridge Rectifier with CMOS Pass Transistors Configuration},
type = {article},
year = {2018},
keywords = {SDG-NMOS,SGS-PMOS,efficiency,full-wave bridge rectifier,leakage power,low power circuit},
volume = {27},
id = {89ee45cf-d5a4-34ca-902f-2e6daa710314},
created = {2018-09-06T11:22:39.932Z},
file_attached = {false},
profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
last_modified = {2018-09-06T11:22:39.932Z},
read = {false},
starred = {false},
authored = {true},
confirmed = {false},
hidden = {false},
private_publication = {false},
abstract = {© 2018 World Scientific Publishing Company. An effortless, more efficient full-wave bridge rectifier is introduced with minimum distortion. Efficient and exploratory combinations of CMOS logic are not only utilized to design full-wave bridge rectifier, but also as pass transistors configurations at the input. The particular CMOS logic (used to design core rectifier circuit) is a collective form of SDG-NMOS and SGS-PMOS. SDG-NMOS refers to a shorted drain gate n-channel metal oxide semiconductor. SGS-PMOS refers to shorted gate to source p-channel metal oxide semiconductor. Due to the utilization of renovated MOS configuration after the replacement of the diode, the efficiency of the full-wave bridge rectifier is increased up to 11% compared to p-n junction diode based full wave bridge rectifier. The proposed full wave bridge rectifier is a comparably low power circuit. The proposed CMOS based full-wave bridge rectifier is optimized at 45-nm CMOS technology. Cadence experimental simulation and implementations of the leakage power and efficiency demonstrate better consistency through the proposed circuit.},
bibtype = {article},
author = {Jain, P. and Joshi, A.},
doi = {10.1142/S0218126618500925},
journal = {Journal of Circuits, Systems and Computers},
number = {6}
}
Downloads: 0
{"_id":"o3vZ4zTatZjKn3xYQ","bibbaseid":"jain-joshi-fullwavebridgerectifierwithcmospasstransistorsconfiguration-2018","author_short":["Jain, P.","Joshi, A."],"bibdata":{"title":"Full-Wave Bridge Rectifier with CMOS Pass Transistors Configuration","type":"article","year":"2018","keywords":"SDG-NMOS,SGS-PMOS,efficiency,full-wave bridge rectifier,leakage power,low power circuit","volume":"27","id":"89ee45cf-d5a4-34ca-902f-2e6daa710314","created":"2018-09-06T11:22:39.932Z","file_attached":false,"profile_id":"11ae403c-c558-3358-87f9-dadc957bb57d","last_modified":"2018-09-06T11:22:39.932Z","read":false,"starred":false,"authored":"true","confirmed":false,"hidden":false,"private_publication":false,"abstract":"© 2018 World Scientific Publishing Company. An effortless, more efficient full-wave bridge rectifier is introduced with minimum distortion. Efficient and exploratory combinations of CMOS logic are not only utilized to design full-wave bridge rectifier, but also as pass transistors configurations at the input. The particular CMOS logic (used to design core rectifier circuit) is a collective form of SDG-NMOS and SGS-PMOS. SDG-NMOS refers to a shorted drain gate n-channel metal oxide semiconductor. SGS-PMOS refers to shorted gate to source p-channel metal oxide semiconductor. Due to the utilization of renovated MOS configuration after the replacement of the diode, the efficiency of the full-wave bridge rectifier is increased up to 11% compared to p-n junction diode based full wave bridge rectifier. The proposed full wave bridge rectifier is a comparably low power circuit. The proposed CMOS based full-wave bridge rectifier is optimized at 45-nm CMOS technology. Cadence experimental simulation and implementations of the leakage power and efficiency demonstrate better consistency through the proposed circuit.","bibtype":"article","author":"Jain, P. and Joshi, A.","doi":"10.1142/S0218126618500925","journal":"Journal of Circuits, Systems and Computers","number":"6","bibtex":"@article{\n title = {Full-Wave Bridge Rectifier with CMOS Pass Transistors Configuration},\n type = {article},\n year = {2018},\n keywords = {SDG-NMOS,SGS-PMOS,efficiency,full-wave bridge rectifier,leakage power,low power circuit},\n volume = {27},\n id = {89ee45cf-d5a4-34ca-902f-2e6daa710314},\n created = {2018-09-06T11:22:39.932Z},\n file_attached = {false},\n profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},\n last_modified = {2018-09-06T11:22:39.932Z},\n read = {false},\n starred = {false},\n authored = {true},\n confirmed = {false},\n hidden = {false},\n private_publication = {false},\n abstract = {© 2018 World Scientific Publishing Company. An effortless, more efficient full-wave bridge rectifier is introduced with minimum distortion. Efficient and exploratory combinations of CMOS logic are not only utilized to design full-wave bridge rectifier, but also as pass transistors configurations at the input. The particular CMOS logic (used to design core rectifier circuit) is a collective form of SDG-NMOS and SGS-PMOS. SDG-NMOS refers to a shorted drain gate n-channel metal oxide semiconductor. SGS-PMOS refers to shorted gate to source p-channel metal oxide semiconductor. Due to the utilization of renovated MOS configuration after the replacement of the diode, the efficiency of the full-wave bridge rectifier is increased up to 11% compared to p-n junction diode based full wave bridge rectifier. The proposed full wave bridge rectifier is a comparably low power circuit. The proposed CMOS based full-wave bridge rectifier is optimized at 45-nm CMOS technology. Cadence experimental simulation and implementations of the leakage power and efficiency demonstrate better consistency through the proposed circuit.},\n bibtype = {article},\n author = {Jain, P. and Joshi, A.},\n doi = {10.1142/S0218126618500925},\n journal = {Journal of Circuits, Systems and Computers},\n number = {6}\n}","author_short":["Jain, P.","Joshi, A."],"biburl":"https://bibbase.org/service/mendeley/11ae403c-c558-3358-87f9-dadc957bb57d","bibbaseid":"jain-joshi-fullwavebridgerectifierwithcmospasstransistorsconfiguration-2018","role":"author","urls":{},"keyword":["SDG-NMOS","SGS-PMOS","efficiency","full-wave bridge rectifier","leakage power","low power circuit"],"metadata":{"authorlinks":{}},"downloads":0},"bibtype":"article","biburl":"https://bibbase.org/service/mendeley/11ae403c-c558-3358-87f9-dadc957bb57d","dataSources":["2252seNhipfTmjEBQ"],"keywords":["sdg-nmos","sgs-pmos","efficiency","full-wave bridge rectifier","leakage power","low power circuit"],"search_terms":["full","wave","bridge","rectifier","cmos","pass","transistors","configuration","jain","joshi"],"title":"Full-Wave Bridge Rectifier with CMOS Pass Transistors Configuration","year":2018}