@article{
 title = {Low leakage and high CMRR CMOS differential amplifier for biomedical application},
 type = {article},
 year = {2017},
 keywords = {Differential amplifier,Efficiency,Gate cross-coupled NMOS transistors,Leakage power,Low power circuit,Pull-up and pull-down stacked transistors},
 volume = {93},
 id = {cb8c6a1e-516c-3ccf-81cd-29d901977f70},
 created = {2018-09-06T11:22:39.870Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:39.870Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2017, Springer Science+Business Media, LLC. A novel, competent, effortless, low leakage CMOS differential amplifier is explored with minimum deformation and proper power utilization. The proposed circuit can also represent a CMOS analog front-end (AFE) circuit for portable biomedical signals acquisition system. The proposed circuit is designed with the intention of supply the power either from VDDto VOUTor from VSSto VOUT. The proposed circuit has high CMRR. It means that the common mode voltage gain is minimum and differential mode voltage gain is high. The circuit is designed in such a way that the power supply couldn’t reach from VDDto VSSdirectly i.e. the driving power of the circuit couldn’t be short circuited. Due to this, the proposed circuit behaves like a perfect differential amplifier. Competent and speculative combinations of CMOS logic are utilized with cross coupled by Gate terminals of NMOS transistors to provide the better functionality of proposed differential amplifier circuit. The proposed circuit with unique combination of MOS has provided better performance parameters. Due to utilization of modified MOS structure with pull-up and pull-down stacked transistors, gain factor of differential amplifier is increased up to 5 dB with compare to other differential amplifier circuits and leakage power dissipation is reduced up to 49%. Proposed CMOS based differential amplifier is optimized at 45 nm CMOS technology. The simulations have been performed using cadence analog virtuoso spectre simulator. The experimental implementations have been done for analysis of leakage power and efficiency with better consistency through the proposed circuit.},
 bibtype = {article},
 author = {Jain, P. and Joshi, A.M.},
 doi = {10.1007/s10470-017-1027-y},
 journal = {Analog Integrated Circuits and Signal Processing},
 number = {1}
}

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The proposed circuit can also represent a CMOS analog front-end (AFE) circuit for portable biomedical signals acquisition system. The proposed circuit is designed with the intention of supply the power either from VDDto VOUTor from VSSto VOUT. The proposed circuit has high CMRR. It means that the common mode voltage gain is minimum and differential mode voltage gain is high. The circuit is designed in such a way that the power supply couldn’t reach from VDDto VSSdirectly i.e. the driving power of the circuit couldn’t be short circuited. Due to this, the proposed circuit behaves like a perfect differential amplifier. Competent and speculative combinations of CMOS logic are utilized with cross coupled by Gate terminals of NMOS transistors to provide the better functionality of proposed differential amplifier circuit. The proposed circuit with unique combination of MOS has provided better performance parameters. Due to utilization of modified MOS structure with pull-up and pull-down stacked transistors, gain factor of differential amplifier is increased up to 5 dB with compare to other differential amplifier circuits and leakage power dissipation is reduced up to 49%. Proposed CMOS based differential amplifier is optimized at 45 nm CMOS technology. The simulations have been performed using cadence analog virtuoso spectre simulator. The experimental implementations have been done for analysis of leakage power and efficiency with better consistency through the proposed circuit.","bibtype":"article","author":"Jain, P. and Joshi, A.M.","doi":"10.1007/s10470-017-1027-y","journal":"Analog Integrated Circuits and Signal Processing","number":"1","bibtex":"@article{\n title = {Low leakage and high CMRR CMOS differential amplifier for biomedical application},\n type = {article},\n year = {2017},\n keywords = {Differential amplifier,Efficiency,Gate cross-coupled NMOS transistors,Leakage power,Low power circuit,Pull-up and pull-down stacked transistors},\n volume = {93},\n id = {cb8c6a1e-516c-3ccf-81cd-29d901977f70},\n created = {2018-09-06T11:22:39.870Z},\n file_attached = {false},\n profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},\n last_modified = {2018-09-06T11:22:39.870Z},\n read = {false},\n starred = {false},\n authored = {true},\n confirmed = {false},\n hidden = {false},\n private_publication = {false},\n abstract = {© 2017, Springer Science+Business Media, LLC. A novel, competent, effortless, low leakage CMOS differential amplifier is explored with minimum deformation and proper power utilization. The proposed circuit can also represent a CMOS analog front-end (AFE) circuit for portable biomedical signals acquisition system. The proposed circuit is designed with the intention of supply the power either from VDDto VOUTor from VSSto VOUT. The proposed circuit has high CMRR. It means that the common mode voltage gain is minimum and differential mode voltage gain is high. The circuit is designed in such a way that the power supply couldn’t reach from VDDto VSSdirectly i.e. the driving power of the circuit couldn’t be short circuited. Due to this, the proposed circuit behaves like a perfect differential amplifier. Competent and speculative combinations of CMOS logic are utilized with cross coupled by Gate terminals of NMOS transistors to provide the better functionality of proposed differential amplifier circuit. The proposed circuit with unique combination of MOS has provided better performance parameters. Due to utilization of modified MOS structure with pull-up and pull-down stacked transistors, gain factor of differential amplifier is increased up to 5 dB with compare to other differential amplifier circuits and leakage power dissipation is reduced up to 49%. Proposed CMOS based differential amplifier is optimized at 45 nm CMOS technology. The simulations have been performed using cadence analog virtuoso spectre simulator. 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