Method, system and device for integration of volatile and non-volatile memory bitcells. Jaiswal, A. R. & Bhargava, M. April~6, 2021. US Patent 10,971,229
bibtex   
@misc{jaiswal2021method,
  title={Method, system and device for integration of volatile and non-volatile memory bitcells},
  author={Jaiswal, Akhilesh Ramlaut and Bhargava, Mudit},
  year={2021},
  month=apr # "~6",
  publisher={Google Patents},
  note={US Patent 10,971,229}
}

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