Rapid Design Space Exploration of Application Specific Heterogeneous Pipelined Multiprocessor Systems. Javaid, H., Ignjatovic, A., & Parameswaran, S. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 29(11):1777-1789, Nov, 2010.
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This paper describes a rapid design methodology to create a pipeline of processors to execute streaming applications. The methodology seeks a system with the smallest area while its runtime is within a specified runtime constraint. Initially, a heuristic is used to rapidly explore a large number of processor configurations to find the near Pareto front of the design space, and then an exact integer linear programming (ILP) formulation (EIF) is used to find an optimal solution. A reduced ILP formulation (RIF) or the heuristic is used if the EIF does not find an optimal solution in a given time window. This design methodology was integrated into a commercial design flow and was evaluated on four benchmarks with design spaces containing up to 1016 design points. For each benchmark, the near Pareto front was found in less than 3 h using the heuristic, while EIF took up to 16 h. The results show that the average area error of the heuristic and RIF was within 2.25% and 1.25% of the optimal design points for all the benchmarks, respectively. The heuristic is faster than RIF, while both the heuristic and RIF are significantly faster than EIF.
@article{ 5605323,
  author = {Javaid, H. and Ignjatovic, A. and Parameswaran, S.},
  journal = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on},
  title = {Rapid Design Space Exploration of Application Specific Heterogeneous Pipelined Multiprocessor Systems},
  year = {2010},
  month = {Nov},
  volume = {29},
  number = {11},
  pages = {1777-1789},
  abstract = {This paper describes a rapid design methodology to create a pipeline of processors to execute streaming applications. The methodology seeks a system with the smallest area while its runtime is within a specified runtime constraint. Initially, a heuristic is used to rapidly explore a large number of processor configurations to find the near Pareto front of the design space, and then an exact integer linear programming (ILP) formulation (EIF) is used to find an optimal solution. A reduced ILP formulation (RIF) or the heuristic is used if the EIF does not find an optimal solution in a given time window. This design methodology was integrated into a commercial design flow and was evaluated on four benchmarks with design spaces containing up to 1016 design points. For each benchmark, the near Pareto front was found in less than 3 h using the heuristic, while EIF took up to 16 h. The results show that the average area error of the heuristic and RIF was within 2.25% and 1.25% of the optimal design points for all the benchmarks, respectively. The heuristic is faster than RIF, while both the heuristic and RIF are significantly faster than EIF.},
  keywords = {Pareto optimisation;integer programming;linear programming;multiprocessing systems;pipeline processing;system-on-chip;application specific heterogeneous pipelined multiprocessor system;integer linear programming formulation;near Pareto front;rapid design space exploration;reduced ILP formulation;runtime constraint;system-on-chip;Design methodology;Multiprocessing systems;Pipelines;Program processors;Runtime;Space exploration;Transform coding;Algorithms;application specific architectures;design space exploration;integer linear programming;multiprocessor system on chip (MPSoC)},
  doi = {10.1109/TCAD.2010.2061353},
  issn = {0278-0070}
}
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