@inproceedings{DBLP:conf/ispan/JeeP02,
  author       = {Sunghyun Jee and
                  Kannappan Palaniappan},
  title        = {Compiler Processor Tradeoffs for {DISVLIW} Architecture},
  booktitle    = {International Symposium on Parallel Architectures, Algorithms and
                  Networks, {ISPAN} 2002, May 22-24, 2002, Makati City, Metro Manila,
                  Philippines},
  pages        = {199--204},
  publisher    = {{IEEE} Computer Society},
  year         = {2002},
  url          = {https://doi.org/10.1109/ISPAN.2002.1004282},
  doi          = {10.1109/ISPAN.2002.1004282},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/ispan/JeeP02.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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