Automated Design Error Localization in RTL Designs. Jenihhin, M., Tšepurov, A., Tihhomirov, V., Raik, J., Hantson, H., Ubar, R., Bartsch, G., Escobar, J. H. M., & Wuttke, H. IEEE Design Test, 31(1):83–92, February, 2014. Conference Name: IEEE Design Testdoi abstract bibtex This paper considers the case where a design described in a Hardware Description Language (HDL) has been identified as erroneous during functional verification and, thus, design error localization is required. However, due to the enormous complexity of modern Register-Transfer Level (RTL) designs, several bugs may escape verification and are consequently handled by post-silicon validation.
@article{jenihhin_automated_2014,
title = {Automated {Design} {Error} {Localization} in {RTL} {Designs}},
volume = {31},
issn = {2168-2364},
doi = {10.1109/MDAT.2013.2271420},
abstract = {This paper considers the case where a design described in a Hardware Description Language (HDL) has been identified as erroneous during functional verification and, thus, design error localization is required. However, due to the enormous complexity of modern Register-Transfer Level (RTL) designs, several bugs may escape verification and are consequently handled by post-silicon validation.},
number = {1},
journal = {IEEE Design Test},
author = {Jenihhin, Maksim and Tšepurov, Anton and Tihhomirov, Valentin and Raik, Jaan and Hantson, Hanno and Ubar, Raimund and Bartsch, Günter and Escobar, Jorge Hernan Meza and Wuttke, Heinz-Dietrich},
month = feb,
year = {2014},
note = {Conference Name: IEEE Design Test},
keywords = {Computer bugs, Design methodology, Error analysis, Hardware design languages, Registers, Verification},
pages = {83--92},
}
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{"_id":"aDZSKf7iXYtzjjbd4","bibbaseid":"jenihhin-tepurov-tihhomirov-raik-hantson-ubar-bartsch-escobar-etal-automateddesignerrorlocalizationinrtldesigns-2014","author_short":["Jenihhin, M.","Tšepurov, A.","Tihhomirov, V.","Raik, J.","Hantson, H.","Ubar, R.","Bartsch, G.","Escobar, J. H. M.","Wuttke, H."],"bibdata":{"bibtype":"article","type":"article","title":"Automated Design Error Localization in RTL Designs","volume":"31","issn":"2168-2364","doi":"10.1109/MDAT.2013.2271420","abstract":"This paper considers the case where a design described in a Hardware Description Language (HDL) has been identified as erroneous during functional verification and, thus, design error localization is required. However, due to the enormous complexity of modern Register-Transfer Level (RTL) designs, several bugs may escape verification and are consequently handled by post-silicon validation.","number":"1","journal":"IEEE Design Test","author":[{"propositions":[],"lastnames":["Jenihhin"],"firstnames":["Maksim"],"suffixes":[]},{"propositions":[],"lastnames":["Tšepurov"],"firstnames":["Anton"],"suffixes":[]},{"propositions":[],"lastnames":["Tihhomirov"],"firstnames":["Valentin"],"suffixes":[]},{"propositions":[],"lastnames":["Raik"],"firstnames":["Jaan"],"suffixes":[]},{"propositions":[],"lastnames":["Hantson"],"firstnames":["Hanno"],"suffixes":[]},{"propositions":[],"lastnames":["Ubar"],"firstnames":["Raimund"],"suffixes":[]},{"propositions":[],"lastnames":["Bartsch"],"firstnames":["Günter"],"suffixes":[]},{"propositions":[],"lastnames":["Escobar"],"firstnames":["Jorge","Hernan","Meza"],"suffixes":[]},{"propositions":[],"lastnames":["Wuttke"],"firstnames":["Heinz-Dietrich"],"suffixes":[]}],"month":"February","year":"2014","note":"Conference Name: IEEE Design Test","keywords":"Computer bugs, Design methodology, Error analysis, Hardware design languages, Registers, Verification","pages":"83–92","bibtex":"@article{jenihhin_automated_2014,\n\ttitle = {Automated {Design} {Error} {Localization} in {RTL} {Designs}},\n\tvolume = {31},\n\tissn = {2168-2364},\n\tdoi = {10.1109/MDAT.2013.2271420},\n\tabstract = {This paper considers the case where a design described in a Hardware Description Language (HDL) has been identified as erroneous during functional verification and, thus, design error localization is required. However, due to the enormous complexity of modern Register-Transfer Level (RTL) designs, several bugs may escape verification and are consequently handled by post-silicon validation.},\n\tnumber = {1},\n\tjournal = {IEEE Design Test},\n\tauthor = {Jenihhin, Maksim and Tšepurov, Anton and Tihhomirov, Valentin and Raik, Jaan and Hantson, Hanno and Ubar, Raimund and Bartsch, Günter and Escobar, Jorge Hernan Meza and Wuttke, Heinz-Dietrich},\n\tmonth = feb,\n\tyear = {2014},\n\tnote = {Conference Name: IEEE Design Test},\n\tkeywords = {Computer bugs, Design methodology, Error analysis, Hardware design languages, Registers, Verification},\n\tpages = {83--92},\n}\n\n","author_short":["Jenihhin, M.","Tšepurov, A.","Tihhomirov, V.","Raik, J.","Hantson, H.","Ubar, R.","Bartsch, G.","Escobar, J. H. M.","Wuttke, H."],"key":"jenihhin_automated_2014","id":"jenihhin_automated_2014","bibbaseid":"jenihhin-tepurov-tihhomirov-raik-hantson-ubar-bartsch-escobar-etal-automateddesignerrorlocalizationinrtldesigns-2014","role":"author","urls":{},"keyword":["Computer bugs","Design methodology","Error analysis","Hardware design languages","Registers","Verification"],"metadata":{"authorlinks":{}},"downloads":0,"html":""},"bibtype":"article","biburl":"https://bibbase.org/zotero/bxt101","dataSources":["Wsv2bQ4jPuc7qme8R"],"keywords":["computer bugs","design methodology","error analysis","hardware design languages","registers","verification"],"search_terms":["automated","design","error","localization","rtl","designs","jenihhin","tšepurov","tihhomirov","raik","hantson","ubar","bartsch","escobar","wuttke"],"title":"Automated Design Error Localization in RTL Designs","year":2014}