A 16nm configurable pass-gate bit-cell register file for quantifying the VMIN advantage of PFET versus NFET pass-gate bit cells. Jeong, J., Atallah, F., Nguyen, H., Puckett, J., Bowman, K. A., & Hansquine, D. In CICC, pages 1-4, 2015. IEEE. Link Paper bibtex @inproceedings{conf/cicc/JeongANPBH15,
added-at = {2015-12-03T00:00:00.000+0100},
author = {Jeong, Jihoon and Atallah, Francois and Nguyen, Hoan and Puckett, Josh and Bowman, Keith A. and Hansquine, David},
biburl = {http://www.bibsonomy.org/bibtex/271325590216ab2d0dc26c9aec7b6fd7a/dblp},
booktitle = {CICC},
crossref = {conf/cicc/2015},
ee = {http://dx.doi.org/10.1109/CICC.2015.7338444},
interhash = {080672bad62c04e2c4ebcc74f2da54d1},
intrahash = {71325590216ab2d0dc26c9aec7b6fd7a},
isbn = {978-1-4799-8682-8},
keywords = {dblp},
pages = {1-4},
publisher = {IEEE},
timestamp = {2015-12-04T11:44:38.000+0100},
title = {A 16nm configurable pass-gate bit-cell register file for quantifying the VMIN advantage of PFET versus NFET pass-gate bit cells.},
url = {http://dblp.uni-trier.de/db/conf/cicc/cicc2015.html#JeongANPBH15},
year = 2015
}
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