@inproceedings{ pradip95,
  author = {Jha, Pradip and Parameswaran, Sri and Dutt, Nikil},
  title = {Reclocking for high level synthesis},
  booktitle = {Asia and South Pacific Design Automation Conference. IFIP International
	Conference on Computer Hardware Description Languages and their Applications.
	IFIP Interntional Conference on Very Large Scale Integration (ASP-DAC'95/CHDL'95/VLSI'95.)},
  year = {1995},
  pages = {49-54},
  address = {Chiba, Japan},
  publisher = {Nihon Gakkai Jimu Senta},
  note = {5217814 high level synthesis reclocking performance improvement wire
	delay consideration bit-width migration library migration feature
	size migration},
  abstract = {Describes a powerful post-synthesis approach called reclocking, for
	performance improvement by minimizing the total execution time. By
	back annotating the wire delays of designs created by a high level
	synthesis system, and then finding an optimal clockwidth, we resynthesize
	the controller to improve performance without altering the datapath.
	Reclocking is versatile and can be applied not only for wire delay
	consideration, but also for bit-width migration, library migration
	and for feature size migration supporting the philosophy of design
	reuse. Experimental results show that with reclocking, the performance
	of the input designs can be improved by as much as 34%},
  keywords = {high level synthesis logic design},
  pdf = {http://www.cse.unsw.edu.au/~sridevan/index_files/00486201.pdf}
}

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