ELURA: A Methodology for Post-Silicon Gate-Level Error Localization Using Regression Analysis. Jindal, A., Kumar, B., Basu, K., & Fujita, M. In 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, VLSID 2018, Pune, India, January 6-10, 2018, pages 410–415, 2018. IEEE Computer Society. Paper doi bibtex @inproceedings{DBLP:conf/vlsid/Jindal0BF18,
author = {Ankit Jindal and
Binod Kumar and
Kanad Basu and
Masahiro Fujita},
title = {{ELURA:} {A} Methodology for Post-Silicon Gate-Level Error Localization
Using Regression Analysis},
booktitle = {31st International Conference on {VLSI} Design and 17th International
Conference on Embedded Systems, {VLSID} 2018, Pune, India, January
6-10, 2018},
pages = {410--415},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/VLSID.2018.99},
doi = {10.1109/VLSID.2018.99},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vlsid/Jindal0BF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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