@inproceedings{
 title = {Low complexity hardware implementation of quantization and CAVLC for H.264 encoder},
 type = {inproceedings},
 year = {2015},
 keywords = {Context Adaption,High Defination,Optimization,Real Time Performance,Scaling},
 id = {4c83f464-34fa-3ba0-bf98-6e0a5b583bef},
 created = {2018-09-06T11:22:40.333Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:40.333Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2014 IEEE. H.264 is the advance video coding standard for the compression and distribution of a video content. It has larger complexity in order to satisfy the demand of high quality video at low bit rate. Moreover, it requires the effective implementation of all its internal blocks. In the paper, we focuses on the implementation of two important blocks for H.264 encoder. We propose low complexity design of quantization and Context Adaptive Variable Length Coding (CAVLC). The quantization process is responsible for scaling down the value of transform coefficients. CAVLC is useful for a bit stream generation and it is adopted from the concept of modified Variable Length Coding (VLC) technique. The efficient architectures are designed for quantization and CAVLC blocks to have parallel and pipeline data processing. They are implemented on Virtex 4 XC4VLX40 FPGA family using VHDL. The synthesized results are obtained with Xilinx ISE 14.2 and resource, device utilization and timing analysis are reported. The results are compared with related work that shows the better real time performance of both blocks.},
 bibtype = {inproceedings},
 author = {Joshi, A.M. and Mishra, V. and Patrikar, R.M.},
 doi = {10.1109/ICCIC.2014.7238382},
 booktitle = {2014 IEEE International Conference on Computational Intelligence and Computing Research, IEEE ICCIC 2014}
}

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Moreover, it requires the effective implementation of all its internal blocks. In the paper, we focuses on the implementation of two important blocks for H.264 encoder. We propose low complexity design of quantization and Context Adaptive Variable Length Coding (CAVLC). The quantization process is responsible for scaling down the value of transform coefficients. CAVLC is useful for a bit stream generation and it is adopted from the concept of modified Variable Length Coding (VLC) technique. The efficient architectures are designed for quantization and CAVLC blocks to have parallel and pipeline data processing. They are implemented on Virtex 4 XC4VLX40 FPGA family using VHDL. The synthesized results are obtained with Xilinx ISE 14.2 and resource, device utilization and timing analysis are reported. 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H.264 is the advance video coding standard for the compression and distribution of a video content. It has larger complexity in order to satisfy the demand of high quality video at low bit rate. Moreover, it requires the effective implementation of all its internal blocks. In the paper, we focuses on the implementation of two important blocks for H.264 encoder. We propose low complexity design of quantization and Context Adaptive Variable Length Coding (CAVLC). The quantization process is responsible for scaling down the value of transform coefficients. CAVLC is useful for a bit stream generation and it is adopted from the concept of modified Variable Length Coding (VLC) technique. The efficient architectures are designed for quantization and CAVLC blocks to have parallel and pipeline data processing. They are implemented on Virtex 4 XC4VLX40 FPGA family using VHDL. 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