@article{journals/tcad/JoyC93,
  added-at = {2016-03-18T00:00:00.000+0100},
  author = {Joy, Donald A. and Ciesielski, Maciej J.},
  biburl = {https://www.bibsonomy.org/bibtex/2bba6475882a1548b91eeeee80b2962fb/dblp},
  ee = {http://dx.doi.org/10.1109/43.229730},
  interhash = {cf61542cbfbd69391a91683829cf0edb},
  intrahash = {bba6475882a1548b91eeeee80b2962fb},
  journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
  keywords = {dblp},
  number = 4,
  pages = {461-472},
  timestamp = {2016-03-19T11:41:58.000+0100},
  title = {Clock period minimization with wave pipelining.},
  url = {http://dblp.uni-trier.de/db/journals/tcad/tcad12.html#JoyC93},
  volume = 12,
  year = 1993
}

{"_id":"w4ArsJz9ZkbiGm4bx","bibbaseid":"joy-ciesielski-clockperiodminimizationwithwavepipelining-1993","authorIDs":["5dcdc5f178619fde010000b3"],"author_short":["Joy, D. A.","Ciesielski, M. J."],"bibdata":{"bibtype":"article","type":"article","added-at":"2016-03-18T00:00:00.000+0100","author":[{"propositions":[],"lastnames":["Joy"],"firstnames":["Donald","A."],"suffixes":[]},{"propositions":[],"lastnames":["Ciesielski"],"firstnames":["Maciej","J."],"suffixes":[]}],"biburl":"https://www.bibsonomy.org/bibtex/2bba6475882a1548b91eeeee80b2962fb/dblp","ee":"http://dx.doi.org/10.1109/43.229730","interhash":"cf61542cbfbd69391a91683829cf0edb","intrahash":"bba6475882a1548b91eeeee80b2962fb","journal":"IEEE Trans. on CAD of Integrated Circuits and Systems","keywords":"dblp","number":"4","pages":"461-472","timestamp":"2016-03-19T11:41:58.000+0100","title":"Clock period minimization with wave pipelining.","url":"http://dblp.uni-trier.de/db/journals/tcad/tcad12.html#JoyC93","volume":"12","year":"1993","bibtex":"@article{journals/tcad/JoyC93,\n added-at = {2016-03-18T00:00:00.000+0100},\n author = {Joy, Donald A. and Ciesielski, Maciej J.},\n biburl = {https://www.bibsonomy.org/bibtex/2bba6475882a1548b91eeeee80b2962fb/dblp},\n ee = {http://dx.doi.org/10.1109/43.229730},\n interhash = {cf61542cbfbd69391a91683829cf0edb},\n intrahash = {bba6475882a1548b91eeeee80b2962fb},\n journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},\n keywords = {dblp},\n number = 4,\n pages = {461-472},\n timestamp = {2016-03-19T11:41:58.000+0100},\n title = {Clock period minimization with wave pipelining.},\n url = {http://dblp.uni-trier.de/db/journals/tcad/tcad12.html#JoyC93},\n volume = 12,\n year = 1993\n}\n\n","author_short":["Joy, D. A.","Ciesielski, M. J."],"key":"journals/tcad/JoyC93","id":"journals/tcad/JoyC93","bibbaseid":"joy-ciesielski-clockperiodminimizationwithwavepipelining-1993","role":"author","urls":{"Link":"http://dx.doi.org/10.1109/43.229730","Paper":"http://dblp.uni-trier.de/db/journals/tcad/tcad12.html#JoyC93"},"keyword":["dblp"],"downloads":0,"html":""},"bibtype":"article","biburl":"http://www.bibsonomy.org/bib/author/Maciej ciesielski?items=1000","creationDate":"2019-11-14T21:24:01.413Z","downloads":0,"keywords":["dblp"],"search_terms":["clock","period","minimization","wave","pipelining","joy","ciesielski"],"title":"Clock period minimization with wave pipelining.","year":1993,"dataSources":["4afdeGY8cGceGP6Kx"]}