NVM-Based FPGA Block RAM With Adaptive SLC-MLC Conversion. Ju, L., Sui, X., Li, S., Zhao, M., Xue, C. J., Hu, J., & Jia, Z. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37(11):2661–2672, 2018.
Paper doi bibtex @article{DBLP:journals/tcad/JuSLZXHJ18,
author = {Lei Ju and
Xiaojin Sui and
Shiqing Li and
Mengying Zhao and
Chun Jason Xue and
Jingtong Hu and
Zhiping Jia},
title = {NVM-Based {FPGA} Block {RAM} With Adaptive {SLC-MLC} Conversion},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2661--2672},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857261},
doi = {10.1109/TCAD.2018.2857261},
timestamp = {Sun, 19 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/JuSLZXHJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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