A DfT Insertion Methodology to Scannable Q-Flop Elements. Juracy, L. R., Moreira, M. T., Kuentzer, F. A., & Amory, A. M. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(8):1609-1612, Aug, 2018. doi abstract bibtex The Q-Flop is an alternative memory element for designs that are prone to metastability. It has been substantially explored by past research work, specially in synchronization schemes. However, there is very limited support to test insertion on these critical components. This brief presents a testable Q-flop cell and a methodology to integrate it to standard synthesis and DfT flows, allowing automated scan insertion using conventional sequential cells and commercial design automation solutions. Experimental results explore the tradeoffs of the proposed cell in terms of silicon area, energy, and power when compared to the original Q-flop.
@ARTICLE{Juracy-tvlsi2018,
author={L. R. Juracy and M. T. Moreira and F. A. Kuentzer and Alexandre M. Amory},
journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
title={A DfT Insertion Methodology to Scannable Q-Flop Elements},
year={2018},
volume={26},
number={8},
pages={1609-1612},
abstract={The Q-Flop is an alternative memory element for designs that are prone to metastability. It has been substantially explored by past research work, specially in synchronization schemes. However, there is very limited support to test insertion on these critical components. This brief presents a testable Q-flop cell and a methodology to integrate it to standard synthesis and DfT flows, allowing automated scan insertion using conventional sequential cells and commercial design automation solutions. Experimental results explore the tradeoffs of the proposed cell in terms of silicon area, energy, and power when compared to the original Q-flop.},
keywords = {async, testing},
doi={10.1109/TVLSI.2018.2821134},
ISSN={1063-8210},
month={Aug}
}
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