Testing The Blade Resilient Asynchronous Template: A Structural Approach. Juracy, L. R. Master's thesis, Escola Politécnica, Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS), Porto Alegre, Brasil, 2018. Advisor: Alexandre de Morais Amory; Co-advisor: Matheus Trevisan Moreira![Testing The Blade Resilient Asynchronous Template: A Structural Approach [pdf]](https://bibbase.org/img/filetypes/pdf.svg "pdf")
Link abstract bibtex 1 download Nowadays, the synchronous circuits design approach is the most used design method since it is highly automated by commercial computer-aided design (CAD) tools. Synchronous designs incorporate timing margins to ensure the correct behavior under the worst-case scenario of process and environmental variations, limiting its clock period optimization and increasing power consumption. On one hand, asynchronous designs present some potential advantages when compared to synchronous ones, such as less power consumption and more data throughput, but they may also suffer with the process and environmental variations. On the other hand, resilient circuits techniques are an alternative to keep the design working in presence of effects of variability. Thus, Blade template has been proposed, combining the advantages of both asynchronous and resilient circuits. The Blade template employs latches in its implementation and supports average-case circuit performance. Independently of the design style (synchronous or asynchronous), during the fabrication process of integrated circuits, some imperfections can occur, causing defects that reduce the fabrication yield. These defective ICs can present a faulty behavior, which produces an output different from the expected, and it must be identified before the circuit commercialization. Test methodologies help to find and diagnose this faulty behavior. Design for Testability (DfT) increases circuit testability by adding a degree of controllability and observability through different test techniques. Scan design is a DfT technique that provides for an external test equipment the access to the internal memory elements of a circuit, allowing test pattern insertion and response comparison. The goal of this work is to propose a fully integrated and automated structural DfT approach using commercial EDA tools and to propose a series of design methods to address the challenges related to testing asynchronous and resilient designs, with focus on Blade template. The proposed DfT flow is evaluated with a criptocore module and a microprocessor. The obtained results for the criptocore module show a fault coverage of 98.17% for stuck-at fault model and 89.37% for path-delay fault model, with an area overhead of 112.16%. The obtained results for the microprocessor show a fault coverage of 96.04% for stuck-at fault model and 99.00% for path-delay fault model, with an area overhead of 50.57%.
@mastersthesis{juracy2018,
author = {Juracy, Leonardo Rezende},
title = {{Testing The Blade Resilient Asynchronous Template: A Structural Approach}},
school = {Escola Politécnica, {Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS)}},
year = 2018,
address = {Porto Alegre, Brasil},
url_link = {http://tede2.pucrs.br/tede2/bitstream/tede/8167/2/LEONARDO%20REZENDE%20JURACY_DIS.pdf},
keywords = {GAPH, design for testability, asynchronous, blade, advised},
abstract = {Nowadays, the synchronous circuits design approach is the most used design method since it is highly automated by commercial computer-aided design (CAD) tools. Synchronous designs incorporate timing margins to ensure the correct behavior under the worst-case scenario of process and environmental variations, limiting its clock period optimization and increasing power consumption. On one hand, asynchronous designs present some potential advantages when compared to synchronous ones, such as less power consumption and more data throughput, but they may also suffer with the process and environmental variations. On the other hand, resilient circuits techniques are an alternative to keep the design working in presence of effects of variability. Thus, Blade template has been proposed, combining the advantages of both asynchronous and resilient circuits. The Blade template employs latches in its implementation and supports average-case circuit performance. Independently of the design style (synchronous or asynchronous), during the fabrication process of integrated circuits, some imperfections can occur, causing defects that reduce the fabrication yield. These defective ICs can present a faulty behavior, which produces an output different from the expected, and it must be identified before the circuit commercialization. Test methodologies help to find and diagnose this faulty behavior. Design for Testability (DfT) increases circuit testability by adding a degree of controllability and observability through different test techniques. Scan design is a DfT technique that provides for an external test equipment the access to the internal memory elements of a circuit, allowing test pattern insertion and response comparison. The goal of this work is to propose a fully integrated and automated structural DfT approach using commercial EDA tools and to propose a series of design methods to address the challenges related to testing asynchronous and resilient designs, with focus on Blade template. The proposed DfT flow is evaluated with a criptocore module and a microprocessor. The obtained results for the criptocore module show a fault coverage of 98.17% for stuck-at fault model and 89.37% for path-delay fault model, with an area overhead of 112.16%. The obtained results for the microprocessor show a fault coverage of 96.04% for stuck-at fault model and 99.00% for path-delay fault model, with an area overhead of 50.57%.},
note = {Advisor: Alexandre de Morais Amory; Co-advisor: Matheus Trevisan Moreira}
}
Downloads: 1
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Independently of the design style (synchronous or asynchronous), during the fabrication process of integrated circuits, some imperfections can occur, causing defects that reduce the fabrication yield. These defective ICs can present a faulty behavior, which produces an output different from the expected, and it must be identified before the circuit commercialization. Test methodologies help to find and diagnose this faulty behavior. Design for Testability (DfT) increases circuit testability by adding a degree of controllability and observability through different test techniques. Scan design is a DfT technique that provides for an external test equipment the access to the internal memory elements of a circuit, allowing test pattern insertion and response comparison. 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