Compiler-directed physical address generation for reducing dTLB power. Kadayif, I., Nath, P., Kandemir, M. T., & Sivasubramaniam, A. In 2004 IEEE International Symposium on Performance Analysis of Systems and Software, March 10-12, 2004, Austin, Texas, USA, Proceedings, pages 161–168, 2004. ![Compiler-directed physical address generation for reducing dTLB power [link]](https://bibbase.org/img/filetypes/link.svg "link")
Paper doi bibtex @inproceedings{kadayif_compiler-directed_2004,
title = {Compiler-directed physical address generation for reducing {dTLB} power},
url = {https://doi.org/10.1109/ISPASS.2004.1291368},
doi = {10.1109/ISPASS.2004.1291368},
booktitle = {2004 {IEEE} {International} {Symposium} on {Performance} {Analysis} of {Systems} and {Software}, {March} 10-12, 2004, {Austin}, {Texas}, {USA}, {Proceedings}},
author = {Kadayif, Ismail and Nath, Partho and Kandemir, Mahmut T. and Sivasubramaniam, Anand},
year = {2004},
pages = {161--168}
}
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