Testability of Sequential Circuits with Multi-Cycle False Path. Kalla, P. & Ciesielski, M. J. In 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pages 322–328, 1997. Paper doi bibtex @inproceedings{DBLP:conf/vts/KallaC97,
author = {Priyank Kalla and
Maciej J. Ciesielski},
title = {Testability of Sequential Circuits with Multi-Cycle False Path},
booktitle = {15th {IEEE} {VLSI} Test Symposium (VTS'97), April 27-May 1, 1997,
Monterey, California, {USA}},
pages = {322--328},
year = {1997},
crossref = {DBLP:conf/vts/1997},
url = {https://doi.org/10.1109/VTEST.1997.600295},
doi = {10.1109/VTEST.1997.600295},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/bib/conf/vts/KallaC97},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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