@inproceedings{DBLP:conf/mwscas/Kassiri17a,
  author       = {Hossein Kassiri},
  title        = {Fully discrete-time neural recording front-ends: Feasibility and design
                  considerations},
  booktitle    = {{IEEE} 60th International Midwest Symposium on Circuits and Systems,
                  {MWSCAS} 2017, Boston, MA, USA, August 6-9, 2017},
  pages        = {369--372},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/MWSCAS.2017.8052937},
  doi          = {10.1109/MWSCAS.2017.8052937},
  timestamp    = {Wed, 25 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/mwscas/Kassiri17a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

{"_id":"LoHC4SjPA7mmsmW7w","bibbaseid":"kassiri-fullydiscretetimeneuralrecordingfrontendsfeasibilityanddesignconsiderations-2017","author_short":["Kassiri, H."],"bibdata":{"bibtype":"inproceedings","type":"inproceedings","author":[{"firstnames":["Hossein"],"propositions":[],"lastnames":["Kassiri"],"suffixes":[]}],"title":"Fully discrete-time neural recording front-ends: Feasibility and design considerations","booktitle":"IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017","pages":"369–372","publisher":"IEEE","year":"2017","url":"https://doi.org/10.1109/MWSCAS.2017.8052937","doi":"10.1109/MWSCAS.2017.8052937","timestamp":"Wed, 25 Mar 2020 00:00:00 +0100","biburl":"https://dblp.org/rec/conf/mwscas/Kassiri17a.bib","bibsource":"dblp computer science bibliography, https://dblp.org","bibtex":"@inproceedings{DBLP:conf/mwscas/Kassiri17a,\n author = {Hossein Kassiri},\n title = {Fully discrete-time neural recording front-ends: Feasibility and design\n considerations},\n booktitle = {{IEEE} 60th International Midwest Symposium on Circuits and Systems,\n {MWSCAS} 2017, Boston, MA, USA, August 6-9, 2017},\n pages = {369--372},\n publisher = {{IEEE}},\n year = {2017},\n url = {https://doi.org/10.1109/MWSCAS.2017.8052937},\n doi = {10.1109/MWSCAS.2017.8052937},\n timestamp = {Wed, 25 Mar 2020 00:00:00 +0100},\n biburl = {https://dblp.org/rec/conf/mwscas/Kassiri17a.bib},\n bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n","author_short":["Kassiri, H."],"key":"DBLP:conf/mwscas/Kassiri17a","id":"DBLP:conf/mwscas/Kassiri17a","bibbaseid":"kassiri-fullydiscretetimeneuralrecordingfrontendsfeasibilityanddesignconsiderations-2017","role":"author","urls":{"Paper":"https://doi.org/10.1109/MWSCAS.2017.8052937"},"metadata":{"authorlinks":{}}},"bibtype":"inproceedings","biburl":"https://dblp.org/pid/156/4834.bib","dataSources":["HcWjwtYE4NCzoYzaQ"],"keywords":[],"search_terms":["fully","discrete","time","neural","recording","front","ends","feasibility","design","considerations","kassiri"],"title":"Fully discrete-time neural recording front-ends: Feasibility and design considerations","year":2017}