@article{ keshtkaran_robust_2014,
  title = {A Robust Adaptive Power Line Interference Canceller {VLSI} Architecture and {ASIC} for Multichannel Biopotential Recording Applications},
  volume = {Early Access Online},
  issn = {1549-7747},
  doi = {10.1109/TCSII.2014.2345302},
  abstract = {This brief presents the {VLSI} architecture and {ASIC} of a robust algorithm for removing power line interference in multichannel biopotential recording. When compared with three similar interference removal methods, the proposed algorithm outperforms in terms of robustness, and interference rejection performance. The proposed {VLSI} architecture is scalable with respect to number of channels and/or harmonics. Further performance optimization is obtained through pipelining and resource sharing techniques. A prototype was implemented in a 65-nm {CMOS} process, and validated against a golden model. Measurement results on different types of signal modalities show an average signal-to-noise ratio ({SNR}) improvement of 31 {dB} for input {SNRs} of -20–20 {dB} and line frequencies of 45–65 Hz.},
  journal = {{IEEE} Transactions on Circuits and Systems {II}: Express Briefs},
  author = {Keshtkaran, M. and Yang, Z.},
  year = {2014},
  file = {IEEE Xplore Full Text PDF:files/3561/Keshtkaran and Yang - 2014 - A Robust Adaptive Power Line Interference Cancelle.pdf:application/pdf},
  url_paper = {files/Keshtkaran and Yang - 2014 - A Robust Adaptive Power Line Interference Cancelle.pdf}
}

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