An efficient self exercising two rail checker. Kia, S. M. & Parameswaran, S. Journal of Microelectronic Systems Integration, 5(3):159-65, 1997. Copyright 1997, IEE 5775447 1070-0056 self exercising two rail checker nonsystematic two rail codes two dimensional self exercising two rail checker TDSETR checker delay
abstract   bibtex   
In this paper, a, new efficient self exercising checker for a class of non-systematic two rail codes is introduced. This proposed checker is called the �Two Dimensional Self Exercising Two Rail checker� (TDSETR checker). The TDSETR checker is used to check non-systematic two rail codes. In this method, the checking is done on line. This method significantly reduces the complexity and delay of checking compared to previous circuits. The high speed and low cost advantages of the TDSETR checker are compared with conventional circuits (e.g., the circuit is 30% of the size and has 1% of the delay of previously reported circuits for 256 bit pair inputs)
@article{ kia972,
  author = {Kia, Seyed M. and Parameswaran, Sri},
  title = {An efficient self exercising two rail checker},
  journal = {Journal of Microelectronic Systems Integration},
  year = {1997},
  volume = {5},
  pages = {159-65},
  number = {3},
  note = {Copyright 1997, IEE 5775447 1070-0056 self exercising two rail checker
	nonsystematic two rail codes two dimensional self exercising two
	rail checker TDSETR checker delay},
  abstract = {In this paper, a, new efficient self exercising checker for a class
	of non-systematic two rail codes is introduced. This proposed checker
	is called the �Two Dimensional Self Exercising Two Rail checker�
	(TDSETR checker). The TDSETR checker is used to check non-systematic
	two rail codes. In this method, the checking is done on line. This
	method significantly reduces the complexity and delay of checking
	compared to previous circuits. The high speed and low cost advantages
	of the TDSETR checker are compared with conventional circuits (e.g.,
	the circuit is 30% of the size and has 1% of the delay of previously
	reported circuits for 256 bit pair inputs)},
  keywords = {built-in self test error detection codes fault diagnosis logic testing}
}

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