Power-aware partitioned cache architectures. Kim, S., Vijaykrishnan, N., Kandemir, M. T., Sivasubramaniam, A., Irwin, M. J., & Geethanjali, E. In Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001, Huntington Beach, California, USA, 2001, pages 64–67, 2001. ![Power-aware partitioned cache architectures [link]](https://bibbase.org/img/filetypes/link.svg "link")
Paper doi bibtex @inproceedings{kim_power-aware_2001,
title = {Power-aware partitioned cache architectures},
url = {https://doi.org/10.1145/383082.383095},
doi = {10.1145/383082.383095},
booktitle = {Proceedings of the 2001 {International} {Symposium} on {Low} {Power} {Electronics} and {Design}, 2001, {Huntington} {Beach}, {California}, {USA}, 2001},
author = {Kim, Soontae and Vijaykrishnan, Narayanan and Kandemir, Mahmut T. and Sivasubramaniam, Anand and Irwin, Mary Jane and Geethanjali, E.},
year = {2001},
pages = {64--67}
}
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