@article{WOS:A1996UG81100002,
abstract = {Finite or Galois fields are used in numerous applications like error
correcting codes, digital signal processing and cryptography. These
applications often require computing exponentiations in GF(2(m)) which
is a very computationally intensive operation, The methods proposed in
the literature achieve exponentiation by iterative methods using
repeated multiplications and the hardware implementations use a number
of Galois field multipliers in parallel resulting in expensive hardware.
In this paper, we present a new algorithm based on a pattern matching
technique for computing exponentiations in GF(2(m)), for values of m
less than or equal to 8. A systolic array processor architecture
was,developed by the authors for performing multiplication and division
in GF(2(m)) in \{[\}13], A similar strategy is proposed in this paper for
achieving exponentiation at the rate of a new result every clock cycle.
A prototype VLSI chip called ACE implementing the proposed architecture
for Galois field GF(2(4)) has been designed and verified using CMOS 2 mu
m technology. The chip can yield a computational rate of 40 million
exponentiations per second.},
address = {345 E 47TH ST, NEW YORK, NY 10017-2394},
author = {Kovac, M and Ranganathan, N},
doi = {10.1109/82.488283},
issn = {1057-7130},
journal = {IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING},
month = apr,
number = {4},
pages = {289--297},
publisher = {IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC},
title = {{ACE: A VLSI chip for Galois field GF(2(m)) based exponentiation}},
type = {Article},
volume = {43},
year = {1996}
}

{"_id":"cFeqqwJzJzzWjpaXQ","bibbaseid":"kovac-ranganathan-aceavlsichipforgaloisfieldgf2mbasedexponentiation-1996","author_short":["Kovac, M","Ranganathan, N"],"bibdata":{"bibtype":"article","type":"Article","abstract":"Finite or Galois fields are used in numerous applications like error correcting codes, digital signal processing and cryptography. These applications often require computing exponentiations in GF(2(m)) which is a very computationally intensive operation, The methods proposed in the literature achieve exponentiation by iterative methods using repeated multiplications and the hardware implementations use a number of Galois field multipliers in parallel resulting in expensive hardware. In this paper, we present a new algorithm based on a pattern matching technique for computing exponentiations in GF(2(m)), for values of m less than or equal to 8. A systolic array processor architecture was,developed by the authors for performing multiplication and division in GF(2(m)) in \\[\\13], A similar strategy is proposed in this paper for achieving exponentiation at the rate of a new result every clock cycle. A prototype VLSI chip called ACE implementing the proposed architecture for Galois field GF(2(4)) has been designed and verified using CMOS 2 mu m technology. The chip can yield a computational rate of 40 million exponentiations per second.","address":"345 E 47TH ST, NEW YORK, NY 10017-2394","author":[{"propositions":[],"lastnames":["Kovac"],"firstnames":["M"],"suffixes":[]},{"propositions":[],"lastnames":["Ranganathan"],"firstnames":["N"],"suffixes":[]}],"doi":"10.1109/82.488283","issn":"1057-7130","journal":"IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING","month":"April","number":"4","pages":"289–297","publisher":"IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC","title":"ACE: A VLSI chip for Galois field GF(2(m)) based exponentiation","volume":"43","year":"1996","bibtex":"@article{WOS:A1996UG81100002,\nabstract = {Finite or Galois fields are used in numerous applications like error\ncorrecting codes, digital signal processing and cryptography. These\napplications often require computing exponentiations in GF(2(m)) which\nis a very computationally intensive operation, The methods proposed in\nthe literature achieve exponentiation by iterative methods using\nrepeated multiplications and the hardware implementations use a number\nof Galois field multipliers in parallel resulting in expensive hardware.\nIn this paper, we present a new algorithm based on a pattern matching\ntechnique for computing exponentiations in GF(2(m)), for values of m\nless than or equal to 8. A systolic array processor architecture\nwas,developed by the authors for performing multiplication and division\nin GF(2(m)) in \\{[\\}13], A similar strategy is proposed in this paper for\nachieving exponentiation at the rate of a new result every clock cycle.\nA prototype VLSI chip called ACE implementing the proposed architecture\nfor Galois field GF(2(4)) has been designed and verified using CMOS 2 mu\nm technology. The chip can yield a computational rate of 40 million\nexponentiations per second.},\naddress = {345 E 47TH ST, NEW YORK, NY 10017-2394},\nauthor = {Kovac, M and Ranganathan, N},\ndoi = {10.1109/82.488283},\nissn = {1057-7130},\njournal = {IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING},\nmonth = apr,\nnumber = {4},\npages = {289--297},\npublisher = {IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC},\ntitle = {{ACE: A VLSI chip for Galois field GF(2(m)) based exponentiation}},\ntype = {Article},\nvolume = {43},\nyear = {1996}\n}\n","author_short":["Kovac, M","Ranganathan, N"],"key":"WOS:A1996UG81100002","id":"WOS:A1996UG81100002","bibbaseid":"kovac-ranganathan-aceavlsichipforgaloisfieldgf2mbasedexponentiation-1996","role":"author","urls":{},"metadata":{"authorlinks":{}}},"bibtype":"article","biburl":"https://bibbase.org/f/rTKwnBhyGKSSptYtt/My Collection.bib","dataSources":["DY3AeP9t2QujfB78L","MpTxM7aR49zFotABd"],"keywords":[],"search_terms":["ace","vlsi","chip","galois","field","based","exponentiation","kovac","ranganathan"],"title":"ACE: A VLSI chip for Galois field GF(2(m)) based exponentiation","year":1996}