@inproceedings{DBLP:conf/islped/KozhikkottuVDR14,
  author    = {Vivek Joy Kozhikkottu and
               Swagath Venkataramani and
               Sujit Dey and
               Anand Raghunathan},
  title     = {Variation tolerant design of a vector processor for recognition, mining
               and synthesis},
  booktitle = {International Symposium on Low Power Electronics and Design, ISLPED'14,
               La Jolla, CA, {USA} - August 11 - 13, 2014},
  pages     = {239--244},
  year      = {2014},
  crossref  = {DBLP:conf/islped/2014},
  url       = {http://doi.acm.org/10.1145/2627369.2627636},
  doi       = {10.1145/2627369.2627636},
  timestamp = {Fri, 25 Nov 2016 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/islped/KozhikkottuVDR14},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

{"_id":"n9N3Wc4G93thMGKEg","bibbaseid":"kozhikkottu-venkataramani-dey-raghunathan-variationtolerantdesignofavectorprocessorforrecognitionminingandsynthesis-2014","downloads":0,"creationDate":"2016-02-09T06:00:32.261Z","title":"Variation tolerant design of a vector processor for recognition, mining and synthesis","author_short":["Kozhikkottu, V. J.","Venkataramani, S.","Dey, S.","Raghunathan, A."],"year":2014,"bibtype":"inproceedings","biburl":"https://dblp.org/pid/74/3747.bib","bibdata":{"bibtype":"inproceedings","type":"inproceedings","author":[{"firstnames":["Vivek","Joy"],"propositions":[],"lastnames":["Kozhikkottu"],"suffixes":[]},{"firstnames":["Swagath"],"propositions":[],"lastnames":["Venkataramani"],"suffixes":[]},{"firstnames":["Sujit"],"propositions":[],"lastnames":["Dey"],"suffixes":[]},{"firstnames":["Anand"],"propositions":[],"lastnames":["Raghunathan"],"suffixes":[]}],"title":"Variation tolerant design of a vector processor for recognition, mining and synthesis","booktitle":"International Symposium on Low Power Electronics and Design, ISLPED'14, La Jolla, CA, USA - August 11 - 13, 2014","pages":"239–244","year":"2014","crossref":"DBLP:conf/islped/2014","url":"http://doi.acm.org/10.1145/2627369.2627636","doi":"10.1145/2627369.2627636","timestamp":"Fri, 25 Nov 2016 00:00:00 +0100","biburl":"https://dblp.org/rec/bib/conf/islped/KozhikkottuVDR14","bibsource":"dblp computer science bibliography, https://dblp.org","bibtex":"@inproceedings{DBLP:conf/islped/KozhikkottuVDR14,\n author = {Vivek Joy Kozhikkottu and\n Swagath Venkataramani and\n Sujit Dey and\n Anand Raghunathan},\n title = {Variation tolerant design of a vector processor for recognition, mining\n and synthesis},\n booktitle = {International Symposium on Low Power Electronics and Design, ISLPED'14,\n La Jolla, CA, {USA} - August 11 - 13, 2014},\n pages = {239--244},\n year = {2014},\n crossref = {DBLP:conf/islped/2014},\n url = {http://doi.acm.org/10.1145/2627369.2627636},\n doi = {10.1145/2627369.2627636},\n timestamp = {Fri, 25 Nov 2016 00:00:00 +0100},\n biburl = {https://dblp.org/rec/bib/conf/islped/KozhikkottuVDR14},\n bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n","author_short":["Kozhikkottu, V. J.","Venkataramani, S.","Dey, S.","Raghunathan, A."],"key":"DBLP:conf/islped/KozhikkottuVDR14","id":"DBLP:conf/islped/KozhikkottuVDR14","bibbaseid":"kozhikkottu-venkataramani-dey-raghunathan-variationtolerantdesignofavectorprocessorforrecognitionminingandsynthesis-2014","role":"author","urls":{"Paper":"http://doi.acm.org/10.1145/2627369.2627636"},"downloads":0},"search_terms":["variation","tolerant","design","vector","processor","recognition","mining","synthesis","kozhikkottu","venkataramani","dey","raghunathan"],"keywords":["dblp"],"authorIDs":[],"dataSources":["QATSsZPCAGgNRpLA3"]}