Variation tolerant design of a vector processor for recognition, mining and synthesis. Kozhikkottu, V. J., Venkataramani, S., Dey, S., & Raghunathan, A. In International Symposium on Low Power Electronics and Design, ISLPED'14, La Jolla, CA, USA - August 11 - 13, 2014, pages 239–244, 2014.
Variation tolerant design of a vector processor for recognition, mining and synthesis [link]Paper  doi  bibtex   
@inproceedings{DBLP:conf/islped/KozhikkottuVDR14,
  author    = {Vivek Joy Kozhikkottu and
               Swagath Venkataramani and
               Sujit Dey and
               Anand Raghunathan},
  title     = {Variation tolerant design of a vector processor for recognition, mining
               and synthesis},
  booktitle = {International Symposium on Low Power Electronics and Design, ISLPED'14,
               La Jolla, CA, {USA} - August 11 - 13, 2014},
  pages     = {239--244},
  year      = {2014},
  crossref  = {DBLP:conf/islped/2014},
  url       = {http://doi.acm.org/10.1145/2627369.2627636},
  doi       = {10.1145/2627369.2627636},
  timestamp = {Fri, 25 Nov 2016 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/islped/KozhikkottuVDR14},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

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