Efficient Statistical Model Checking of Hardware Circuits With Multiple Failure Regions

Efficient Statistical Model Checking of Hardware Circuits With Multiple Failure Regions. Kumar, J. A., Ahmadyan, S. N., & Vasudevan, S. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33(6):945–958, 2014.

Paper doi bibtex

@article{DBLP:journals/tcad/KumarAV14,
  author       = {Jayanand Asok Kumar and
                  Seyed Nematollah Ahmadyan and
                  Shobha Vasudevan},
  title        = {Efficient Statistical Model Checking of Hardware Circuits With Multiple
                  Failure Regions},
  journal      = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
  volume       = {33},
  number       = {6},
  pages        = {945--958},
  year         = {2014},
  url          = {https://doi.org/10.1109/TCAD.2014.2299957},
  doi          = {10.1109/TCAD.2014.2299957},
  timestamp    = {Thu, 24 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tcad/KumarAV14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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