Reconfigurable distributed fault tolerant routing algorithm for on-chip networks. Kumar, M., Srivastava, P. K., Laxmi, V., Gaur, M. S., & Ko, S. In 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013, New York City, NY, USA, October 2-4, 2013, pages 290–295, 2013.
Reconfigurable distributed fault tolerant routing algorithm for on-chip networks [link]Paper  doi  bibtex   
@inproceedings{DBLP:conf/dft/KumarSLGK13,
  author       = {Manoj Kumar and
                  Pankaj Kumar Srivastava and
                  Vijay Laxmi and
                  Manoj Singh Gaur and
                  Seok{-}Bum Ko},
  title        = {Reconfigurable distributed fault tolerant routing algorithm for on-chip
                  networks},
  booktitle    = {2013 {IEEE} International Symposium on Defect and Fault Tolerance
                  in {VLSI} and Nanotechnology Systems, {DFTS} 2013, New York City,
                  NY, USA, October 2-4, 2013},
  pages        = {290--295},
  year         = {2013},
  crossref     = {DBLP:conf/dft/2013},
  url          = {https://doi.org/10.1109/DFT.2013.6653621},
  doi          = {10.1109/DFT.2013.6653621},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dft/KumarSLGK13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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