Modeling and Reliability Evaluation of logic Circuits at Nanoscale. Kumawat, R., Sahula, V., (., J., Gaur, M., S., & Laxmi, V. In 1st IEEE International Workshop on Reliability Aware System Design and Test, 2010.
bibtex   
@inproceedings{
 title = {Modeling and Reliability Evaluation of logic Circuits at Nanoscale},
 type = {inproceedings},
 year = {2010},
 id = {4636f367-7516-36d1-9c8b-7cf2a2595930},
 created = {2014-04-17T21:17:22.000Z},
 file_attached = {false},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {kumawat2010rasdat},
 source_type = {inproceedings},
 private_publication = {false},
 bibtype = {inproceedings},
 author = {Kumawat, R. and Sahula, Vineet (MNIT Jaipur) and Gaur, M S and Laxmi, V},
 booktitle = {1st IEEE International Workshop on Reliability Aware System Design and Test}
}

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