@inproceedings{conf/cicc/KuoHDYLTHWH14,
  added-at = {2014-11-16T00:00:00.000+0100},
  author = {Kuo, Ming-Zhang and Hsieh, Henry and Dhong, Sang H. and Yang, Ping-Lin and Lin, Cheng-Chung and Tseng, Ryan and Huang, Kevin and Wang, Min-Jer and Hwang, Wei},
  biburl = {https://www.bibsonomy.org/bibtex/21bc2948904154b3b739f96991fef2138/dblp},
  booktitle = {CICC},
  crossref = {conf/cicc/2014},
  ee = {http://dx.doi.org/10.1109/CICC.2014.6946030},
  interhash = {0bf954340f136c06b1076ba068362d2d},
  intrahash = {1bc2948904154b3b739f96991fef2138},
  keywords = {dblp},
  pages = {1-4},
  publisher = {IEEE},
  timestamp = {2015-06-18T19:51:13.000+0200},
  title = {A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS.},
  url = {http://dblp.uni-trier.de/db/conf/cicc/cicc2014.html#KuoHDYLTHWH14},
  year = 2014
}

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