Design of a power/performance efficient single-loop sigma-delta modulator for wireless receivers. Kusu, A.; Borodenkov, A.; Ismail, M.; and Tenhunen, H. Volume 3254 , 2004.
abstract   bibtex   
In order to design high performance sigma-delta A/D converters, it is essential to estimate the Figure-Of-Merit in the design process. This paper describes the design of a power/performance efficient single-loop multibit sigmadelta modulator for wireless applications. Power dissipation is minimized by optimizing the architecture and by a careful design of analog circuitry. A 3 rd order 4-bit ∑-Δ modulator with feedforward path is designed in 0.18um CMOS process operating from 1.8V supply voltage. The modulator dissipates 8.6 mW and achieves a dynamic range of 84/95 dB over a bandwidth of 2000/100 kHz. © Springer-Verlag 2004.
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 title = {Design of a power/performance efficient single-loop sigma-delta modulator for wireless receivers},
 type = {book},
 year = {2004},
 source = {Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)},
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 abstract = {In order to design high performance sigma-delta A/D converters, it is essential to estimate the Figure-Of-Merit in the design process. This paper describes the design of a power/performance efficient single-loop multibit sigmadelta modulator for wireless applications. Power dissipation is minimized by optimizing the architecture and by a careful design of analog circuitry. A 3 rd  order 4-bit ∑-Δ modulator with feedforward path is designed in 0.18um CMOS process operating from 1.8V supply voltage. The modulator dissipates 8.6 mW and achieves a dynamic range of 84/95 dB over a bandwidth of 2000/100 kHz. © Springer-Verlag 2004.},
 bibtype = {book},
 author = {Kusu, A. and Borodenkov, A. and Ismail, M. and Tenhunen, H.}
}
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