MGSim—Simulation tools for multi-core processor architectures. Lankamp, M., Poss, R., Yang, Q., Fu, J., Uddin, I., & Jesshope, C. R. Technical Report arXiv:1302.1390v1 [cs.AR], University of Amsterdam, February, 2013.
MGSim—Simulation tools for multi-core processor architectures [link]Paper  MGSim—Simulation tools for multi-core processor architectures [pdf]Local  abstract   bibtex   
MGSim is an open source discrete event simulator for on-chip hardware components, developed at the University of Amsterdam. It is intended to be a research and teaching vehicle to study the fine-grained hardware/software interactions on many-core and hardware multithreaded processors. It includes support for core models with different instruction sets, a configurable multi-core interconnect, multiple configurable cache and memory models, a dedicated I/O subsystem, and comprehensive monitoring and interaction facilities. The default model configuration shipped with MGSim implements Microgrids, a many-core architecture with hardware concurrency management. MGSim is furthermore written mostly in C++ and uses object classes to represent chip components. It is optimized for architecture models that can be described as process networks.

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