Enabling shared memory communication in networks of MPSoCs. Lant, J., Concatto, C., Attwood, A., Pascual, J., A., Ashworth, M., Navaridas, J., Luján, M., & Goodacre, J. Concurrency and Computation: Practice and Experience, 0(0):e4774.
Enabling shared memory communication in networks of MPSoCs [link]Website  abstract   bibtex   
Summary Ongoing transistor scaling and the growing complexity of embedded system designs has led to the rise of MPSoCs (Multi-Processor System-on-Chip), combining multiple hard-core CPUs and accelerators (FPGA, GPU) on the same physical die. These devices are of great interest to the supercomputing community, who are increasingly reliant on heterogeneity to achieve power and performance goals in these closing stages of the race to exascale. In this paper, we present a network interface architecture and networking infrastructure, designed to sit inside the FPGA fabric of a cutting-edge MPSoC device, enabling networks of these devices to communicate within both a distributed and shared memory context, with reduced need for costly software networking system calls. We will present our implementation and prototype system and discuss the main design decisions relevant to the use of the Xilinx Zynq Ultrascale+, a state-of-the-art MPSoC, and the challenges to be overcome given the device's limitations and constraints. We demonstrate the working prototype system connecting two MPSoCs, with communication between processor and remote memory region and accelerator. We then discuss the limitations of the current implementation and highlight areas of improvement to make this solution production-ready.
@article{
 title = {Enabling shared memory communication in networks of MPSoCs},
 type = {article},
 identifiers = {[object Object]},
 keywords = {FPGA,HPC,MPSoC,distributed shared memory,interconnect,networks},
 pages = {e4774},
 volume = {0},
 websites = {https://onlinelibrary.wiley.com/doi/abs/10.1002/cpe.4774},
 id = {7c340ef3-b471-3d93-a080-a866d6cc56ce},
 created = {2019-05-21T07:49:26.751Z},
 file_attached = {false},
 profile_id = {3b531ebc-e490-366b-8004-15c8c731a6be},
 group_id = {165bb104-ad0f-3683-906f-c36a29c720bb},
 last_modified = {2019-05-21T07:49:26.751Z},
 read = {false},
 starred = {false},
 authored = {false},
 confirmed = {true},
 hidden = {false},
 citation_key = {doi:10.1002/cpe.4774},
 source_type = {article},
 notes = {e4774 cpe.4774},
 private_publication = {false},
 abstract = {Summary Ongoing transistor scaling and the growing complexity of embedded system designs has led to the rise of MPSoCs (Multi-Processor System-on-Chip), combining multiple hard-core CPUs and accelerators (FPGA, GPU) on the same physical die. These devices are of great interest to the supercomputing community, who are increasingly reliant on heterogeneity to achieve power and performance goals in these closing stages of the race to exascale. In this paper, we present a network interface architecture and networking infrastructure, designed to sit inside the FPGA fabric of a cutting-edge MPSoC device, enabling networks of these devices to communicate within both a distributed and shared memory context, with reduced need for costly software networking system calls. We will present our implementation and prototype system and discuss the main design decisions relevant to the use of the Xilinx Zynq Ultrascale+, a state-of-the-art MPSoC, and the challenges to be overcome given the device's limitations and constraints. We demonstrate the working prototype system connecting two MPSoCs, with communication between processor and remote memory region and accelerator. We then discuss the limitations of the current implementation and highlight areas of improvement to make this solution production-ready.},
 bibtype = {article},
 author = {Lant, Joshua and Concatto, Caroline and Attwood, Andrew and Pascual, Jose A and Ashworth, Mike and Navaridas, Javier and Luján, Mikel and Goodacre, John},
 journal = {Concurrency and Computation: Practice and Experience},
 number = {0}
}

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