A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS. Lee, H., Yun, W., Choi, Y., Choi, H., Lee, J., Kim, K., Kang, S., Yang, J., Kang, J., Lee, H., Lee, D., Sim, S., Kim 0001, Y., Choi, W., Song, K., Shin, S., Moon, H., Kwack, S., Lee, J., Park, N., Kim, K., Choi, Y., Ahn, J., & Chung, B. In Proceedings of International Solid-State Circuits Conference (ISSCC), pages 140-141, 2009. ![A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS [link]](https://bibbase.org/img/filetypes/link.svg "link")
Paper bibtex @inproceedings{ dblp3210028,
title = {A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS},
author = {Hyun-Woo Lee and Won-Joo Yun and Young-Kyoung Choi and Hyang-Hwa Choi and Jong-Jin Lee and Ki-Han Kim and Shin-Deok Kang and Ji-Yeon Yang and Jae-Suck Kang and Hyeng-Ouk Lee and Dong-Uk Lee and Sujeong Sim and Young-Ju Kim 0001 and Won-Jun Choi and Keun-Soo Song and Sang-Hoon Shin and Hyung-Wook Moon and Seung-Wook Kwack and Jung-Woo Lee and Nak-Kyu Park and Kwan-Weon Kim and Young-Jung Choi and Jin-Hong Ahn and Byong-Tae Chung},
author_short = {Lee, H. and Yun, W. and Choi, Y. and Choi, H. and Lee, J. and Kim, K. and Kang, S. and Yang, J. and Kang, J. and Lee, H. and Lee, D. and Sim, S. and Kim 0001, Y. and Choi, W. and Song, K. and Shin, S. and Moon, H. and Kwack, S. and Lee, J. and Park, N. and Kim, K. and Choi, Y. and Ahn, J. and Chung, B.},
bibtype = {inproceedings},
type = {inproceedings},
year = {2009},
key = {dblp3210028},
id = {dblp3210028},
biburl = {http://www.dblp.org/rec/bibtex/conf/isscc/LeeYCCLKKYKLLSKCSSMKLPKCAC09},
url = {http://dx.doi.org/10.1109/ISSCC.2009.4977347},
conference = {ISSCC},
pages = {140-141},
text = {ISSCC 2009:140-141},
booktitle = {Proceedings of International Solid-State Circuits Conference (ISSCC)}
}
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