An all-digital architecture for low-jitter regulated delay lines. Levantino, S., Zanuso, M., Tasca, D., Samori, C., & Lacaita, A. L. In Proceedings of International Conference on Environmental and Computer Science (ICECS), pages 603-606, 2009. Paper bibtex @inproceedings{ dblp2185796,
title = {An all-digital architecture for low-jitter regulated delay lines},
author = {Salvatore Levantino and Marco Zanuso and Davide Tasca and Carlo Samori and Andrea L. Lacaita},
author_short = {Levantino, S. and Zanuso, M. and Tasca, D. and Samori, C. and Lacaita, A. L.},
bibtype = {inproceedings},
type = {inproceedings},
year = {2009},
key = {dblp2185796},
id = {dblp2185796},
biburl = {http://www.dblp.org/rec/bibtex/conf/icecsys/LevantinoZTSL09},
url = {http://dx.doi.org/10.1109/ICECS.2009.5410855},
conference = {ICECS},
pages = {603-606},
text = {ICECS 2009:603-606},
booktitle = {Proceedings of International Conference on Environmental and Computer Science (ICECS)}
}
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