Exploring Low Temperature Poly-Si for Low Cost and Low Power Sub-micron Digital Operation

Exploring Low Temperature Poly-Si for Low Cost and Low Power Sub-micron Digital Operation. Li, J., Bansal, A., & Roy, K. In 2006 64th Device Research Conference (<strong>DRC</strong>), pages 61–62, June, 2006.
doi bibtex

@INPROCEEDINGS{li2006drc, 
author={Li, Jing and Bansal, Aditya and Roy, Kaushik}, 
booktitle={2006 64th Device Research Conference (<strong>DRC</strong>)}, 
title={Exploring Low Temperature {Poly-Si} for Low Cost and Low Power Sub-micron Digital Operation}, 
year={2006}, 
volume={}, 
number={}, 
pages={61--62}, 
keywords={conference, Costs,Crystallization,Dielectric substrates,Digital circuits,Fabrication,Grain boundaries,Grain size,Silicon,Temperature,Thin film transistors}, 
doi={10.1109/DRC.2006.305118}, 
ISSN={1548-3770}, 
month={June},
}

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