Novel Variation-Aware Circuit Design of Scaled LTPS TFT for Ultra low Power, Low-Cost Applications

Novel Variation-Aware Circuit Design of Scaled LTPS TFT for Ultra low Power, Low-Cost Applications. Li, J., Kang, K., & Roy, K. In 2007 IEEE International Conference on Integrated Circuit Design and Technology (<strong>ICICDT</strong>), pages 1–4, May, 2007.
doi bibtex

@INPROCEEDINGS{li2007icicdt, 
author={Jing Li and Kunhyuk Kang and Kaushik Roy}, 
booktitle={2007 IEEE International Conference on Integrated Circuit Design and Technology (<strong>ICICDT</strong>)}, 
title={Novel Variation-Aware Circuit Design of Scaled {LTPS TFT} for Ultra low Power, Low-Cost Applications}, 
year={2007}, 
volume={}, 
number={}, 
pages={1--4}, 
keywords={conference, digital integrated circuits,elemental semiconductors,flexible electronics,grain boundaries,integrated circuit design,low-power electronics,response surface methodology,silicon,thin film transistors,Si,battery-operated portable electronics,defect grain boundary region,device-to-device variation,flexible substrate,low-cost digital design,low-temperature polycrystalline silicon thin film transistors,multifinger parallel structure,power dissipation,response surface method,scaled LTPS TFT,size 200 nm,statistical variation,variation-aware circuit design,voltage 10 V to 20 V,Circuit synthesis,Digital circuits,Flexible printed circuits,Glass,Grain boundaries,Polymers,Silicon,Substrates,Temperature,Thin film transistors,Low-temperature polycrystalline-Silicon (LTPS),Response Surface Method (RSM),grain boundary (GB),thin film transistor (TFT)}, 
doi={10.1109/ICICDT.2007.4299589}, 
ISSN={2381-3555}, 
month={May},}

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